A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

There is provided a data processing apparatus, which is suitable for verifying memory systems. Processing circuitry issues a plurality of memory access requests to a plurality of addresses in a memory. Point-of-trust circuitry receives the memory access requests from the processing circuitry via a first set of intermediate circuits. Secure channel circuitry enables secure communication of a correspondence between the plurality of addresses from the processing circuitry to the point-of-trust circuitry. The point-of-trust circuitry determines whether the addresses in the memory of the memory access requests received via the first set of intermediate circuits have a predetermined relationship based on the correspondence.

A non-volatile memory device includes a memory cell array including a plurality of memory cells respectively connected to a plurality of word lines; a plurality of first pass transistors each connected to one side of one of the plurality of word lines; a plurality of second pass transistors each connected to the other side of one of the plurality of word lines; a voltage generator configured to generate a plurality of operating voltages and to apply the plurality of operating voltages to the memory cell array; in response to a first switch control signal, a first switch circuit configured to connect the plurality of first pass transistors to the voltage generator; and in response to a first switch control signal, a second switch circuit configured to connect the plurality of second pass transistors to the voltage generator.

The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.

A semiconductor device includes: a first transfer path outputting a first preliminary signal; a second transfer path outputting a second preliminary signal; a third transfer path outputting a third preliminary signal; a first calibration circuit generating a first calibration code corresponding to a difference in delay values between the first transfer path and a selected transfer path having a largest delay value among the first to third transfer paths; a second calibration circuit generating a second calibration code corresponding to a difference in delay values between the second transfer path and the selected transfer path; a third calibration circuit generating a third calibration code corresponding to a difference in delay values between the third transfer path and the selected transfer path; a first delay control circuit generating a first signal; a second delay control circuit generating a second signal; and a third delay control circuit generating a third signal.

Methods, systems, and devices for monitoring and adjusting access operations at a memory device are described to support integrating monitors or sensors for detecting memory device health issues, such as those resulting from device access or wear. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a metric related to access operations for the memory device. The memory device may use the metric (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.

A memory system includes a resistive nonvolatile memory array configured to store data and error correction code (ECC) bits and a memory controller. The memory controller is configured to detect a number of errors among the stored look-ahead bits, compare the number of look-ahead bit errors to a threshold number of bit errors, perform a strong refresh of the data and look-ahead bits stored in the resistive nonvolatile memory array when the number of look-ahead bit errors equals or exceeds the threshold, and perform a weak refresh of the data and look-ahead bits by refreshing only units of stored data having data bit errors and look-ahead bits having look-ahead bit errors when the number of look-ahead bit errors is less than the threshold.

A memory system includes a resistive nonvolatile memory array configured to store data and error correction code (ECC) bits and a memory controller. The memory controller is configured to detect a number of errors among the stored look-ahead bits, compare the number of look-ahead bit errors to a threshold number of bit errors, perform a strong refresh of the data and look-ahead bits stored in the resistive nonvolatile memory array when the number of look-ahead bit errors equals or exceeds the threshold, and perform a weak refresh of the data and look-ahead bits by refreshing only units of stored data having data bit errors and look-ahead bits having look-ahead bit errors when the number of look-ahead bit errors is less than the threshold.

Embodiments of a memory, and calibration and operation methods thereof for reading data in memory cells are disclosed. In an example, first data from a plurality of memory cells is sensed, each of the first data corresponding to a first bit. Measurements of first currents converted from voltages of the first data are obtained. Second data from the plurality of memory cells is sensed, each of the second data corresponding to a second bit which is different from the first bit. Measurements of second currents converted from voltages of the second data are obtained. One or more parameters corresponding to one or more components of a charge sharing circuit are adjusted until each of a plurality of reference currents provided by a plurality of transistors is within a predetermined range of a nominal value determined based on the measurements of first currents and the measurements of second currents.

A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy desired characteristics is provided. The semiconductor device includes a memory cell, a bit line pair being coupled to the memory cell and having a voltage changed towards a power-supply voltage and a ground voltage in accordance with data of the memory cell in a read mode, and a specifying circuit for specifying a bit line out of the bit line pair. In the semiconductor device, a wiring capacitance is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between a power voltage and a ground voltage in a test mode.