A system and method for centrally logging and aggregating miscompares on chip during a memory test. The method includes performing, by a built-in self-test (BIST) unit of a memory device, a memory test on one or more memory banks of the memory device using a first algorithm. The method includes generating miscompare results responsive to performing the memory test on the one or more memory banks of the memory device. The method includes determining failure diagnostic information based on the miscompare results. The method includes generating an error packet comprising the failure diagnostic information and the miscompare results. The method includes placing the error packet in a queue of a plurality of error packets to generate a queued error packet.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

A system for outputting test data from cores to one communication interface. The system includes shared memories corresponding to the cores. Each shared memory includes a ring buffer and an array of slots. Each core generates a diagnostic message, and stores the generated diagnostic message in a select memory region of the ring buffer corresponding to a first empty slot of the array of slots. A selected core finds a first diagnostic message among diagnostic messages stored in the shared memories, and outputs the first diagnostic message to a personal computer through the communication interface.

A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.

A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal mode other than the test mode using the parallel bit operation.

A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal mode other than the test mode using the parallel bit operation.

Apparatuses, systems, and methods related to determination of a match between data values stored by three or more arrays are described. A system using the data values may manage performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on whether the data values match. For instance, one apparatus described herein includes a plurality of arrays of memory cells formed on a single memory chip. The apparatus further includes comparator circuitry configured to compare data values stored by three arrays selected from the plurality to determine whether there is a match between the data values stored by the three arrays. The apparatus further includes an output component configured to output data values of one of two arrays of the three arrays responsive to determination of the match between the data values stored by the two arrays.

Apparatuses, systems, and methods related to determination of a match between data values stored by three or more arrays are described. A system using the data values may manage performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on whether the data values match. For instance, one apparatus described herein includes a plurality of arrays of memory cells formed on a single memory chip. The apparatus further includes comparator circuitry configured to compare data values stored by three arrays selected from the plurality to determine whether there is a match between the data values stored by the three arrays. The apparatus further includes an output component configured to output data values of one of two arrays of the three arrays responsive to determination of the match between the data values stored by the two arrays.

A built-in self test (BIST) may be performed on a device memory having two memory portions that are symmetrical (e.g., two symmetric halves of the device memory). The BIST may be run on the first memory portion. Error logic output from the first memory portion is captured (stored) in the second memory portion during the BIST run process. Error logic output from the first memory portion may include error data and an address of the memory error in the first memory portion. As the first and second memory portions are symmetric, the memory errors captured (stored) in the second memory portion are located at identical locations to the location of the memory errors in the first memory portion. A memory dump from the second memory portion after the BIST may provide a map of the memory errors in the first memory portion.

A memory system includes a plurality of memory devices having respective arrays of memory cells therein, a bus electrically coupled to and shared by the plurality of memory devices, and a memory controller. The memory controller, which is electrically coupled to the bus, includes a built-in self-test (BIST) circuit, which is commonly connected to the plurality of memory devices. The BIST circuit is configured to transfer a command set including a test pattern to the plurality of memory devices via the bus, and transfer a command trigger signal for driving the test pattern to the plurality of memory devices via the bus.