A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal.

Systems and methods presented herein provide for monitoring block, page, and/or stripe degradation. In one embodiment, a controller is operable to scan a first block of memory to identify a failure in a portion of the first block. The controller suspends input/output (I/O) operations to the failed portion of the first block, and tests the failed portion of the first block to determine if the failure is a transient failure. Testing includes loading the portion of the first block with data, and reading the data from the loaded portion of the first block. If the failure subsides after testing, the controller is further operable to determine that the failure is a transient failure, and to resume I/O operations to the portion of the first block.

Systems and methods presented herein provide for monitoring block, page, and/or stripe degradation. In one embodiment, a controller is operable to scan a first block of memory to identify a failure in a portion of the first block. The controller suspends input/output (I/O) operations to the failed portion of the first block, and tests the failed portion of the first block to determine if the failure is a transient failure. Testing includes loading the portion of the first block with data, and reading the data from the loaded portion of the first block. If the failure subsides after testing, the controller is further operable to determine that the failure is a transient failure, and to resume I/O operations to the portion of the first block.

A method for operating a memory includes determining to perform an error correction operation; determining whether to perform an error correction operation; generating an internal address when the error correction operation is performed; reading data from memory cells that are selected based on the internal address and an error correction code corresponding to the data; performing an error correction operation on the data based on the error correction code to produce an error-corrected data; writing the error-corrected data and an error correction code corresponding to the error-corrected data into the memory cells; determining one or more regions among regions in the memory as a repair-requiring region based on an error detected when the error correction operation is performed; receiving a first command; backing up the data and the error correction code into a redundant region in response to the first command; and repairing the repair-requiring region with the redundant region.

A method for operating a memory includes determining to perform an error correction operation; determining whether to perform an error correction operation; generating an internal address when the error correction operation is performed; reading data from memory cells that are selected based on the internal address and an error correction code corresponding to the data; performing an error correction operation on the data based on the error correction code to produce an error-corrected data; writing the error-corrected data and an error correction code corresponding to the error-corrected data into the memory cells; determining one or more regions among regions in the memory as a repair-requiring region based on an error detected when the error correction operation is performed; receiving a first command; backing up the data and the error correction code into a redundant region in response to the first command; and repairing the repair-requiring region with the redundant region.

A method and apparatus of integrating memory stacks includes providing a first memory die of a first memory technology and a second memory die of a second memory technology. A first logic die is in communication with the first memory die of the first memory technology, and includes a first memory controller including a first memory control function for interpreting requests in accordance with a first protocol for the first memory technology. A second logic die is in communication with the second memory die of the second memory technology and includes a second memory controller including a second memory control function for interpreting requests in accordance with a second protocol for the second memory technology. A memory operation request is received at the first or second memory controller, and the memory operation request is performed in accordance with the associated first memory protocol or the second memory protocol.

A repair device and a semiconductor device including the same are disclosed, which relate to a technology for storing failure information in a fuse circuit during a test operation. The repair device includes a test circuit configured to test data received from a cell array in response to a test signal, and output a failure signal when a failure occurs. The repair device also includes a count circuit configured to output a counting signal by counting the failure signal, a column failure decision circuit configured to determine whether a column failure occurs in response to the counting signal, and output a write enable signal. Further, the repair device includes a fuse controller configured to output a failed column address in response to the counting signal when the write enable signal is activated, and a column fuse circuit configured to sequentially store the column address.

A repair device and a semiconductor device including the same are disclosed, which relate to a technology for storing failure information in a fuse circuit during a test operation. The repair device includes a test circuit configured to test data received from a cell array in response to a test signal, and output a failure signal when a failure occurs. The repair device also includes a count circuit configured to output a counting signal by counting the failure signal, a column failure decision circuit configured to determine whether a column failure occurs in response to the counting signal, and output a write enable signal. Further, the repair device includes a fuse controller configured to output a failed column address in response to the counting signal when the write enable signal is activated, and a column fuse circuit configured to sequentially store the column address.

A method of using on-chip circuitry to test a memory of a chip is provided. The method including, in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one, and in the capture stage, passing the values from each respective first stage latch through compression logic of the first n-bit compression structure to output a single compressed address value, providing the single compressed address value to a second stage latch of the first n-bit compression structure.

A method of using on-chip circuitry to test a memory of a chip is provided. The method including, in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one, and in the capture stage, passing the values from each respective first stage latch through compression logic of the first n-bit compression structure to output a single compressed address value, providing the single compressed address value to a second stage latch of the first n-bit compression structure.