Devices, systems and methods for improving a decoding operation in a non-volatile memory are described. An example method includes performing a first hard read to obtain a first set of values stored in a plurality of cells, storing the first set of values in a first buffer, performing a plurality of subsequent hard reads on the plurality of cells to obtain a plurality of subsequent sets of values, performing, for each subsequent set of values, the following operations: computing a quality metric, storing, in a second buffer, a difference between the subsequent set of values and the set of values stored in the first buffer, wherein the difference is stored in a compressed format, and storing, in response to the quality metric exceeding a threshold, the subsequent set of values in the first buffer, and generating, based on the first buffer and the second buffer, the log-likelihood ratio.

An on-chip memory diagnostic (OCMD) circuit may instruct a set of built-in self-test (BIST) engines to execute BIST on memories associated with the set of BIST engines. Next, results of executing BIST on the memories may be received from the set of BIST engines. A set of memory failures may then be identified in the memories based on the results. Next, one or more BIST engines in the set of BIST engines may be instructed to collect diagnostic data for each memory failure. A set of diagnostic data may then be received for the set of memory failures. Next, the set of diagnostic data may be stored in an on-chip data container. The set of diagnostic data may then be provided via a communication channel.

A storage device for generating an identity code and an identity code generating method are disclosed. The storage device includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores a plurality of first data and the first data have a plurality of bits. The second storage circuit stores a plurality of second data and the second data have a plurality of bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, selects a first portion of the first data according to the first sequence, reads the first portion of the first data from the first storage circuit to form a target sequence and outputs the target sequence to serve as an identity code.

A storage device for generating an identity code and an identity code generating method are disclosed. The storage device includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores a plurality of first data and the first data have a plurality of bits. The second storage circuit stores a plurality of second data and the second data have a plurality of bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, selects a first portion of the first data according to the first sequence, reads the first portion of the first data from the first storage circuit to form a target sequence and outputs the target sequence to serve as an identity code.

Various examples described herein are directed to systems and methods for generating data values using a NAND flash array. A memory controller may read a number of memory cells at the NAND flash array using an initial read level to generate a first raw string. The memory controller may determine that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value and read the number of memory cells using a second read level to generate a second raw string. The memory controller may determine that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than a threshold value and applying a cryptographic function using the second raw string to generate a first PUF value.

Devices, systems and methods for improving a decoding operation in a non-volatile memory are described. An example method includes performing a first hard read to obtain a first set of values stored in a plurality of cells, storing the first set of values in a first buffer, performing a plurality of subsequent hard reads on the plurality of cells to obtain a plurality of subsequent sets of values, performing, for each subsequent set of values, the following operations: computing a quality metric, storing, in a second buffer, a difference between the subsequent set of values and the set of values stored in the first buffer, wherein the difference is stored in a compressed format, and storing, in response to the quality metric exceeding a threshold, the subsequent set of values in the first buffer, and generating, based on the first buffer and the second buffer, the log-likelihood ratio.

Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

A memory system includes a non-volatile memory and a controller. The controller is configured to, during a writing operation, generate a first error-detecting code from data that is input, perform a predetermined conversion on the data into first conversion data, generate a second error-detecting code from the first conversion data, and store the data, the first error-detecting code, and the second-error detecting code in the non-volatile memory. The controller is configured to during a read operation, read the data, the first error-detecting code, and the second error-detecting code from the non-volatile memory, perform a first error detection on the data using the first error-detecting code, perform the predetermined conversion on the data into second conversion data, perform a second error detection on the second conversion data using the second error-detecting code, and output the second conversion data based on results of the first and second error detections.

A system, comprising: a plurality of first latches; a compressor circuit, coupled to the first latches, configured to compress an first signal having X bits from the first latches to a second signal having Y bits, wherein X and Y are positive integers and X is larger than Y; and at least one second latch, coupled to the compressor circuit, configured to receive the second signal to generate a scan output, wherein each of the first latches and the second latch forms a D flip flop. The system outputs the first signal but none of the scan output in a normal mode, and outputs the scan output but none of the first signal in a test mode.