Memory devices may have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices may use an address scrambler to determine a bit error rate for accessing memory cells and remap an address of a particular memory cell to have a bit error rate below a threshold. In this way, the address scrambler may distribute the bit error rates of multiple accesses of the array.

Apparatus and method for replacing portions of a quantum circuit with multi-qubit gates. For example, one embodiment of an apparatus comprises: a quantum circuit analyzer to evaluate an original quantum circuit specification including one or more sub-circuits of the original quantum circuit specification, the quantum circuit analyzer to generate results of the evaluation; a quantum circuit generator to generate a new quantum circuit specification based on the results of the evaluation generated by the quantum circuit analyzer, the quantum circuit generator to generate the new quantum circuit specification by, at least in part, replacing the one or more sub-circuits of the original quantum circuit specification with one or more multi-qubit gates.

The present technology may include a first storage circuit connected to a plurality of memory banks, an error correction circuit, a read path including a plurality of sub-read paths connected between the plurality of memory banks and the error correction circuit, and a control circuit configured to control data output from the plurality of memory banks to be simultaneously stored in the first storage circuit by deactivating the read path during a first sub-test section, and to control the data stored in the first storage circuit to be sequentially transmitted to the error correction circuit by sequentially activating the plurality of sub-read paths during a second sub-test section.

A memory controller includes a memory interface and a processor. The processor is coupled to the memory interface and controls access operation of a memory device via the memory interface. The processor maintains a predetermined table according to write operation of a first memory block of the memory device and performs data protection in response to the write operation. When performing the data protection, the processor determines whether memory space damage has occurred in the first memory block. When it is determined that memory space damage has occurred in the first memory block, the processor traces back one or more data sources of data written in the first memory block according to the predetermined table to obtain address information of one or more source memory blocks and performs a data recovery operation according to the address information of the one or more source memory blocks.

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.

An apparatus includes a storage area signal generation circuit configured to generate a storage area signal when performing an internal information storage operation and an external information storage operation; and an information storage circuit configured to receive internal failure information, stored in the apparatus, based on the storage area signal and store the received internal failure information as failure information in a set storage capacity, and store external failure information, applied from outside the apparatus, as the failure information in a variable storage capacity.

Exemplary methods, apparatuses, and systems include receiving a plurality of read operations. The read operations are divided into a current set of a sequence of read operations and one or more other sets. The size of the current set is a first number of read operations. An aggressor read operation is selected from the current set. A data integrity scan is performed on a victim of the aggressor and a first indicator of data integrity is determined based on the first data integrity scan. A size of a subsequent set of read operations is set to a second number, which less than the first number, based on the indicator of data integrity.

A signal generation circuit includes: a clock circuit configured to receive a flag signal and generate a clock signal; a control circuit configured to generate a control circuit; and a generation circuit connected to both the clock circuit and control circuit and configured to receive the clock signal, the control signal, and the flag signal and generate a target signal, wherein when the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level, and after the target signal is maintained at the fourth level for a target duration, the target signal changes from the fourth level to the third level; and the generation circuit is further configured to determine the target duration according to the clock signal and control signal.

A signal generation circuit includes: a clock module, configured to generate a clock signal based on a flag signal; a control module, configured to generate a control signal according to number of transitions of the clock signal within a fixed time; and a generation module, respectively connected to the clock module and the control module, and configured to receive the clock signal, the control signal, and the flag signal, and to generate a target signal. When the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level. After being maintained at the fourth level for a target duration, the target signal changes from the fourth level to the third level. The generation module is further configured to determine the target duration according to the clock signal and the control signal.