A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.

An apparatus may include an address counter to provide first address information and second address information. The first address information may include a first number of bits and the second address information may include a second number of bits that is smaller than the first number of bits. The address counter may perform a first updating operation. The first updating operation being such that the first address information is updated from a first initial value to a first final value. The address counter may also perform a second updating operation, the second updating operation being such that the second address information is updated from a second initial value to a second final value. In addition, the address counter may also perform the second updating operation at least twice per the first updating operation being performed once.

A semiconductor device includes a soft repair control circuit configured to generate an enable signal, in response to a soft repair control signal, wherein the enable signal is enabled when first and second internal addresses counted in a refresh operation have the same combination as first and second failure addresses, and the semiconductor device also includes a core circuit including first, second, third, and fourth regions each including a plurality of word lines which are activated based on a combination of the first, the second, third, and fourth internal addresses, wherein the core circuit is configured to repair, in response to the enable signal, a word line in which a failure has occurred and which is included in a region selected among the first, second, third, and fourth regions by the third and fourth internal addresses.

Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.

Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.

An apparatus may include an address counter to provide first address information and second address information. The first address information may include a first number of bits and the second address information may include a second number of bits that is smaller than the first number of bits. The address counter may perform a first updating operation. The first updating operation being such that the first address information is updated from a first initial value to a first final value. The address counter may also perform a second updating operation, the second updating operation being such that the second address information is updated from a second initial value to a second final value. In addition, the address counter may also perform the second updating operation at least twice per the first updating operation being performed once.

A semiconductor device includes a soft repair control circuit configured to generate an enable signal, in response to a soft repair control signal, wherein the enable signal is enabled when first and second internal addresses counted in a refresh operation have the same combination as first and second failure addresses, and the semiconductor device also includes a core circuit including first, second, third, and fourth regions each including a plurality of word lines which are activated based on a combination of the first, the second, third, and fourth internal addresses, wherein the core circuit is configured to repair, in response to the enable signal, a word line in which a failure has occurred and which is included in a region selected among the first, second, third, and fourth regions by the third and fourth internal addresses.

Providing efficient handling of memory array failures in processor-based systems is disclosed. In this regard, in one aspect, a memory controller of a processor-based device is configured to detect a defect within a memory element of a plurality of memory elements of a memory array. In response, a disable register of one or more disable registers is set to correspond to the memory element to indicate that the memory element is disabled. The memory controller receives a memory access request to a memory address corresponding to the memory element, and determines, based on one or more disable registers, whether the memory element is disabled. If so, the memory controller disallows the memory access request. Some aspects may provide that the memory controller, in response to detecting the defect, provides a failure indication to an executing process, and subsequently receives, from the executing process, a request to set the disable register.

A DRAM device with embedded flash memory for redundancy is disclosed. The DRAM device includes a substrate having a DRAM array area and a peripheral area. The peripheral area includes an embedded flash forming region and a first transistor forming region. DRAM cells are disposed within the DRAM array area. Flash memory is disposed in the embedded flash forming region. The flash memory includes an ONO storage structure and a flash memory gate structure. A first transistor is disposed in the first transistor forming region.

A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.