G01N2021/8864

Multi-Parameter Inspection Apparatus for Monitoring of Manufacturing Parts
20230258578 · 2023-08-17 ·

Additive manufacturing, such as laser sintering or melting of additive layers, can produce parts rapidly at small volume and in a factory setting. To ensure the additive manufactured parts are of high quality, a real-time non-destructive evaluation (NDE) technique is required to detect defects while they are being manufactured. The present invention describes an in-situ (real-time) inspection unit that can be added to an existing additive manufacturing (AM) tool, such as an FDM (fused deposition modeling) machine, or a direct metal laser sintering (DMLS) machine, providing real-time information about the part quality, and detecting flaws as they occur. The information provided by this unit is used to a) qualify the part as it is being made, and b) to provide feedback to the AM tool for correction, or to stop the process if the part will not meet the quality, thus saving time, energy and reduce material loss.

Print check repeater defect detection

Systems and methods for detecting defects on a reticle are provided. One system includes computer subsystem(s) configured for performing at least one repeater defect detection step in front-end processing during an inspection process performed on a wafer having features printed in a lithography process using a reticle. The at least one repeater defect detection step performed in the front-end processing includes identifying any defects detected at corresponding locations in two or more test images by double detection and any defects detected by stacked defect detection as first repeater defect candidates. One or more additional repeater defect detections may be performed on the first repeater defect candidates to generate final repeater defect candidates and identify defects on the reticle from the final repeater defect candidates.

CARE AREA BASED DEFECT DETECTION

There is provided a system and method of assisting defect detection on a semiconductor specimen. The method includes obtaining a first map informative of multiple care areas (CAs) to be inspected on a die; creating a plurality of bounding rectangles (BRs) enclosing the multiple CAs; and compacting the plurality of BRs to a set of compacted rectangles to meet a predefined inspection capacity while attempting to minimize a non-CA area enclosed by the set of compacted rectangles, giving rise to a second map informative of the set of compacted rectangles. The compaction comprises constructing an R-tree structure representative of the plurality of BRs and compacted rectangles, and selecting a set of nodes from the R-tree structure based on the predefined inspection capacity and representative of the set of compacted rectangles. The second map is usable for filtering a defect map indicative of defect candidate distribution on the die.

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND NON- TRANSITORY COMPUTER-READABLE STORAGE MEDIUM
20220136979 · 2022-05-05 ·

This invention provides an information processing apparatus comprising an image creating unit which creates, from a first image associated with global coordinates, a partial image that is a portion of the first image, as a second image, a recognition processing unit which executes, on the second image, recognition processing of a preset characteristic, and creates a recognition result associated with local coordinates of the second image, and a coordinate converting unit which converts the coordinates of the recognition result from the local coordinates into the global coordinates.

Intelligent defect identification system

Various defects in an electronic assembly can be intelligently identified with a system having at least a server connected to a first capture module and a second capture module. The first capture module may be positioned proximal a first manufacturing line while the second capture module is positioned proximal a second manufacturing line. Images can be collected of first and second electronic assemblies by respective first and second capture modules prior to the images being sent to a classification module of the server where at least one defect is automatically detected in each of the first and second electronic assemblies concurrently with the classification module.

ULTRASOUND VIBRATING-TYPE DEFECT DETECTION APPARATUS AND WIRE DEFECT DETECTION SYSTEM

An ultrasound vibrating-type defect detection apparatus (100) for detecting a defect in a semiconductor apparatus (10) is provided with: an ultrasound vibrator (42); a high-frequency power supply (40); a camera (45); and a controller (50) for adjusting the frequency of high-frequency power supplied from the high-frequency power supply (40) to the ultrasound vibrator (42), and for performing detection of a defect in the semiconductor apparatus (10). The controller (50) causes the camera (45) to capture an image of the semiconductor apparatus (10) while varying the frequency of high-frequency power supplied from the high-frequency power supply (40) to the ultrasound vibrator (42), and performs detection of a defect in the semiconductor apparatus (10) on the basis of the captured image.

Method for performing smart semiconductor wafer defect calibration
11719650 · 2023-08-08 · ·

A smart conversion and calibration of the defect coordinate, diagnosis, sampling system and the method thereof for manufacturing fab are provided. The intelligent defect diagnosis method includes receiving pluralities of defect data, design layout data, analyzing the defect data, design layouts, by a Critical Area Analysis (CAA) system. The method utilizes the precisely calibrated coordinate, the defect layout pattern, and the higher accurate calibrated defect size value. So, a more precise killer defect index can be generated with calibrated coordinate deviation calibration and defect size deviation calibration. When judging a defect relating to short circuit or open circuit failure probability, the defect failure result is more accurate and less incorrect judgment.

CRACK EVALUATION APPARATUS, CRACK EVALUATION METHOD, AND CRACK EVALUATION PROGRAM
20220148150 · 2022-05-12 · ·

The crack evaluation apparatus includes a crack information acquiring unit that performs image processing on a captured image of a structure and acquires crack information about cracks of the structure; a crack vector generating unit that generates crack vectors on the basis of the acquired crack information, and generates, among the crack vectors that are generated, a coupling crack vector coupling, according to a coupling standard, crack vectors that are spatially separated from each other; a display unit that displays, in a classified manner, the crack vectors and the coupling crack vector that are generated; an operating unit that accepts a user operation for editing the crack vectors and the coupling crack vector that are displayed; and an evaluation unit that acquires an evaluation result of the cracks of the structure on the basis of crack information of the crack vectors and the coupling crack vector that are edited.

Smart defect calibration system in semiconductor wafer manufacturing
11761904 · 2023-09-19 · ·

A smart conversion and calibration of the defect coordinate, diagnosis, sampling system and the method thereof for manufacturing fab is provided. The intelligent defect diagnosis method includes receiving pluralities of defect data, design layout data, analyzing the defect data, design layouts, by a Critical Area Analysis (CAA) system. This method utilizes the precisely calibrated coordinate, the defect layout pattern, and the higher accurate calibrated defect size value. So, a more precise killer defect index can be generated with calibrated coordinate deviation calibration and defect size deviation calibration. When judging a defect relating to short circuit or open circuit failure probability, the defect failure result is more accurate and less incorrect judgment.

Method for semiconductor wafer inspection and system thereof

A method for semiconductor wafer inspection is provided. The method includes the following operations. The semiconductor wafer is scanned to acquire a scanned map, wherein the semiconductor wafer is patterned according to a design map having a programmed defect. The design map and the scanned map are transformed to a transformed inspection map according to the location of the programmed defect on the design map and the location of the programmed defect on the scanned map. The system of semiconductor wafer inspection is also provided.