Patent classifications
G01R1/045
WAVE INTERFACE ASSEMBLY FOR AUTOMATIC TEST EQUIPMENT FOR SEMICONDUCTOR TESTING
Embodiments of the present disclosure utilize customizable waveguide fabrication technologies (e.g., 3D printer technology) and patch antenna arrays to create adaptable wave interfaces that can provide efficient signal routing for an ATE system. In this fashion, embodiments of the present disclosure allow for arbitrary waveguide routing from port to port and create high density port spacing at the PCB level and which specifically eliminates the large flange required of prior art waveguides. Furthermore, embodiments include the ability to integrate different waveguide components, including power splitters, couplers, terminations, etc., into a single structure. Thus, embodiments of the present disclosure can reduce signal path losses and simplify the mechanical construction of ATE systems while eliminating the need for coax cables and minimizing the length of PCB microstrips.
HYBRID SHIELDING SOCKETS WITH IMPEDANCE TUNING FOR INTEGRATED CIRCUIT DEVICE TEST TOOLING
High frequency operation of an integrated circuit test system is greatly extended by incorporation of a dedicated high frequency signal element that provides a circuit specific compensation network as part of the intermediation circuit board that enables connectivity between test equipment and the integrated circuit under test.
Inspection device
A first signal line pattern has one end electrically connected to a first connector. A second signal line pattern has one end electrically connected to a second connector. The second signal line pattern has the other end facing the other end of the first signal line pattern. A conductive block has a convex portion. The convex portion of the conductive block is electrically connected to a third portion of the conductive pattern positioned between the other end of the first signal line pattern and the other end of the second signal line pattern of the wiring board.
Coaxial socket of impedance matching structure for semiconductor chip testing and manufacturing method thereof
The present invention relates to a coaxial socket of an impedance matching structure for semiconductor chip testing and a manufacturing method thereof. The coaxial socket includes a test socket locating substrate, a test socket body, a test socket cover, and a test probe. A polymer I and a polymer II are installed and fastened in the test socket body and the test socket cover respectively. A probe slot I and a probe slot II are provided in the polymer I and the polymer II respectively. The test probe is inserted through the probe slot I and the probe slot II. In the present invention, the test socket body and the test socket cover are made of conductive metal, and single-end impedance matching of 50 ohms or differential impedance matching of 100 ohms is performed between them and the probe, to achieve superb signal transmission and heat conduction.
CAPACITOR IN SOCKET
The present invention provides for an improved method and structure for forming an electrical interconnects mechanism in a Power Distribution Network (PDN) by placing capacitors on the top of the pin array on the printed circuit board (PCB) of the structure to decouple the PDN and results in lower impedance benefitting the frequency range of the PDN effecting a significant performance improvement in the spring-pin inductance from the transmission line. This reduction in impedance reduces the power supply ripple.
COAXIAL TRANSMISSION LINE SLI SOCKET DESIGNS FOR 224GBS AND BEYOND
In an embodiment, a socket comprises a housing, where the housing is a dielectric material. In an embodiment, a shell passes through a thickness of the, where the shell is conductive. The socket may further comprise a plug within the shell, where the plug is a dielectric material, and where the plug has a bottom surface. In an embodiment, a pin passes through the thickness of the housing within an inner diameter of the shell, where the pin has a first portion with a first diameter and a second portion with a second diameter, and where the pin is conductive. In an embodiment, the socket further comprises a spring around the first portion of the pin, where a first end of the spring presses against the bottom surface, and where a second end of the spring presses against the second portion of the pin.
Waveguide integrated circuit testing
A structure and method for providing a housing which includes a high frequency (HF) connection between a device under test (DUT) having a wave port 20 and a load board via a waveguide structure. The waveguide includes a wave insert 42, a waveguide adapter 24 and a conductive compliant member 40 which maintains bias between the adapter 24 and the DUT HF port 20 while also maintaining an RF shield despite the variable height of the DUT wave port. The adapter may also include a projection 64 which is received in a recess in the waveguide so that the shielding between the waveguide and adapter has full integrity.
TEST EQUIPMENT FOR TESTING A DEVICE UNDER TEST HAVING A CIRCUIT COUPLED TO AN ANTENNA
Devices for testing a DUT having a circuit coupled to an antenna are disclose. The device can include a DUT location, a probe, and a ground area configured to serve as an antenna ground area for the antenna of the DUT. The ground area includes a slot that the antenna feed impedance is not affected or not affected significantly. The probe is adapted to weakly couple to the antenna of the DUT via the opening to probe a signal when the antenna of the DUT is fed by the circuit of the DUT and/or in order to couple a signal to the antenna which is fed to the circuit of the DUT by the antenna.
Test socket
A test socket includes a pedestal. The pedestal includes a central pedestal including a central contact portion coming in contact with a central region of a bottom surface of a semiconductor package and a plurality of insertion holes formed to correspond to a plurality of solder balls projecting from the bottom surface of the semiconductor package, so as to allow the solder balls to be inserted into respective insertion holes. The pedestal further includes a circumferential pedestal separated from the central pedestal by a space having an opening width larger than a diameter of the insertion hole and including a circumferential contact portion coming in contact with a circumference of the bottom surface of the semiconductor package.
Test equipment for testing a device under test having a circuit coupled to an antenna
Devices for testing a DUT having a circuit coupled to an antenna are disclose. The device can include a DUT location, a probe, and a ground area configured to serve as an antenna ground area for the antenna of the DUT. The ground area includes a slot that the antenna feed impedance is not affected or not affected significantly. The probe is adapted to weakly couple to the antenna of the DUT via the opening to probe a signal when the antenna of the DUT is fed by the circuit of the DUT and/or in order to couple a signal to the antenna which is fed to the circuit of the DUT by the antenna.