A method of calibrating a thermal sensor device is provided. The method includes extracting an incremental voltage to temperature curve for a diode array from a first incremental voltage of the diode array at a first temperature. The diode array and a device under test (DUT) which includes a thermal sensor are heated. After heating the diode array, a first incremental temperature is determined from the incremental voltage to temperature curve for the diode array and a second incremental voltage of the diode array after heating the diode array. An incremental voltage to temperature curve is extracted for the DUT from the first incremental temperature, a first incremental voltage for the DUT at the first temperature, and a second incremental voltage of the DUT after heating the device under test. A temperature error for the thermal sensor is determined from the incremental voltage to temperature curve for the DUT.

A semiconductor package test apparatus includes an interface board having connection terminals for electrically connecting a semiconductor package to a tester, a push block for pressing the semiconductor package toward the interface board to bring external terminals of the semiconductor package into contact with the connection terminals of the interface board, a temperature adjustment unit connected with the push block to heat or cool the semiconductor package to a test temperature through the push block, and a heat transfer member for thermally connecting the push block and the interface board.

A stand-alone active thermal interposer device for use in testing a system-in-package device under test (DUT), the active thermal interposer device includes a body layer having a first surface and a second surface, wherein the first surface is operable to be disposed adjacent to a cold plate, and a plurality of heating zones defined across a second surface of the body layer, the plurality of heating zones operable to be controlled by a thermal controller to selectively heat and maintain respective temperatures thereof, the plurality of heating zones operable to heat a plurality of areas of the DUT when the second surface of the body layer is disposed adjacent to an interface surface of the DUT during testing of the DUT.

A system and method introduce a variable thermal resistance to test and burn in apparatus. The system and method provide an efficient design for more accurate temperature control of integrated circuits. A system for testing integrated circuit (IC) packages comprises a plurality of IC testing socket bases arranged on a testing board and configured to receive a plurality of IC packages. A plurality of IC testing socket lids are arranged to attach to the testing board. Each IC testing socket lid comprises a temperature sensor to thermally contact the IC package and measure a surface temperature of the IC package, a heat sink is placed into either proximity to or directly in contact with the IC package, and an electronic controller to receive signals from the temperature sensor. A variable thermal resistance is introduced in the thermal conductive pathway formed from the device under test (DUT), the DUT contact and the heat sink such that the heat introduced into the system can be controlled and the adverse effects of unwanted cooling can be mitigated.

A test socket assembly for a semiconductor device used for burn-in testing comprising a base assembly, a floating plate coupled to the base assembly, and a latch assembly mounted on the floating plate for the retention and movement of the semiconductor device. The base assembly further includes a pin assembly for electrically coupling to the semiconductor device for burn-in testing and at least two upstanding flex arms. In addition, the floating plate and the latch assembly move to a test position for accommodating a varying height of the semiconductor device when mating with a test fixture while the latch still effectively retains the semiconductor device. Lastly, the floating plate is held in a fixed load position due to the support provided by the upstanding flex arms when inserting the semiconductor device into the test socket.

A thermal test head for an integrated circuit device includes a heat exchanger assembly, a contact assembly configured to contact the integrated circuit, and a thermal control assembly disposed between the heat exchanger assembly and the contact assembly. The thermal control assembly includes a Peltier device in thermal contact with opposing surfaces of the heat exchanger assembly and the contact assembly, and a spacer in physical contact with the opposing surfaces of the heat exchanger assembly and the contact assembly.

A thermal test head for an integrated circuit device includes a heat exchanger assembly, a contact assembly configured to contact the integrated circuit, and a thermal control assembly disposed between the heat exchanger assembly and the contact assembly. The thermal control assembly includes a Peltier device in thermal contact with opposing surfaces of the heat exchanger assembly and the contact assembly, and a spacer in physical contact with the opposing surfaces of the heat exchanger assembly and the contact assembly.

A test apparatus and an automatic test equipment having the same are disclosed. The test apparatus includes a test head having a test area, a socket board combined to the test area of the test, the socket board including a socket body and an active device attached on a first surface of the socket body, the active device configured to operate a semiconductor package, and a heat exchanger arranged on an upper portion of the test head, the heat exchanger being in contact with the socket board.

Systems for probing superconducting circuits, including using a non-magnetic cryogenic heater, are disclosed. A system including a circuit board having a socket and a heater, mounted on the socket, is provided. The heater includes a resistive element and an arrangement for connection with wires configured to supply a current to the resistive element, where the heater is non-magnetic. The system further includes an integrated circuit package, mounted on the socket, such that the heater is located between the socket and the package, where the integrated circuit comprises superconducting circuits having a first temperature corresponding to a superconducting transition temperature. The heater is configured to raise a temperature associated with the integrated circuit from a second temperature to the first temperature, where the second temperature is lower than the first temperature, and where each of the first temperature and the second temperature is a cryogenic temperature.

Apparatus and methods provide burn-in testing for semiconductors. A burn-in test apparatus (1) may include an outer housing forming an aperture with a test socket to receive a tile or wafer. The tile or wafer may include semiconductor device(s) for burn-in testing. The apparatus may include a thermal control unit to regulate testing temperature and/or drive electronics for powering the socket. The apparatus may include an inlet for gas pressure from a pressure source. The apparatus may include a lid covering the aperture when a tile/wafer is at the test socket. The apparatus may include a seal carrier in the aperture to form a pressure chamber with a surface of the tile. The pressure chamber may pneumatically couple with the inlet. Pressure of the pressure chamber may act upon the tile/wafer to urge a device under testing into thermal and/or electrical contact with the socket for conducting the burn-in test.