One example includes a cryogenic wafer test system. The system includes a first chamber that is cooled to a cryogenic temperature and a wafer chuck confined within the first chamber. The wafer chuck can be configured to accommodate a wafer device-under-test (DUT) comprising a plurality of superconducting die. The system also includes a second chamber that is held at a non-cryogenic temperature and which comprises a wafer chuck actuator system configured to provide at least one of translational and rotational motion of the wafer chuck via mechanical linkage interconnecting the wafer chuck and the wafer chuck actuator system. The system further includes a radiation barrier arranged between the first chamber and the second chamber and through which the mechanical linkage extends, the radiation barrier being configured to provide a thermal gradient between the cryogenic temperature of the first chamber and the non-cryogenic temperature of the second chamber.

A system for testing a semiconductor may include a transfer chamber, at least one loadlock chamber and at least one test chamber. The transfer chamber may include a plurality of sidewalls. The loadlock chamber may be arranged on a first sidewall of the sidewalls of the transfer chamber. The loadlock chamber may include a carrier configured to receive a plurality of wafers. The test chamber may be arranged on a second sidewall of the sidewalls of the transfer chamber. When the transfer chamber is connected to the loadlock chamber, a pressure of the transfer chamber may be changed into a pressure of the loadlock chamber. When the transfer chamber is connected to the test chamber, the pressure of the transfer chamber may be changed into a pressure of the test chamber.

A test board includes a board substrate, a connector at a side of the board substrate, a plurality of device-under-test (DUT) boards which are connected to the board substrate and on which semiconductor devices are mounted as DUTs, and a plurality of DC-DC converters connected to the plurality of DUT boards. The plurality of DC-DC converters convert an input voltage supplied thereto via the connector into operating voltages, and provide the operating voltages to the semiconductor devices on the plurality of DUT boards corresponding thereto. The operating voltages are substantially the same.

A failure analysis unit is a wafer conveyance unit configured to convey a wafer while holding the wafer in a semiconductor failure analysis apparatus, the wafer conveyance unit including: a placement table configured to fix a wafer at a predetermined observation position; and a wafer chuck configured to convey the wafer while holding the wafer to the observation position. The wafer chuck includes a plurality of holding members (protruding portions) provided so as to face a side surface of the wafer, and holds the wafer by sandwiching a peripheral portion of the wafer W with the plurality of holding members.

A wafer inspection apparatus according to one embodiment is a wafer inspection apparatus including a plurality of inspection parts arranged in a height direction and a lateral direction, and includes a pair of air circulating means disposed at both ends in a longitudinal direction of an air circulating region including the plurality of inspection parts arranged in the lateral direction and configured to circulate air in the circulating region.

A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.

A sensor test apparatus having excellent versatility is provided. The sensor test apparatus includes a first application unit 40 including a first application device including a socket to which the sensor is electrically connected, and a pressure chamber 43 which applies pressure to the sensor, a test unit which tests the sensor 90 via the socket, a conveying robot which conveys the sensor into and out of the first application unit 40, and an apparatus main body which houses the first application unit 40, the test unit 35 and the conveying robot, and the apparatus main body has an opening which allows the first application unit 40 to be inserted into the apparatus main body and removed from the apparatus main body to an outside.

The present invention relates to a chip tray positioning device, which mainly comprises a frame body, a tray conveying module, a pulling module, a pushing module and a controller. The tray conveying module is disposed on the frame body, electrically connected to the controller and controlled to convey a chip tray from the start area to the end area. The pulling module and the pushing module are disposed on the frame body, electrically connected to the controller and controlled to cause the chip tray to be abutted against the end wall and the lateral wall of the frame body, thereby realizing the positioning of the chip tray and eliminating an error formed in the transfer process of the chip tray. In addition, the controller also controls the pushing module to knock the chip tray at a specific frequency so that the chip tray is vibrated.

A stand-alone active thermal interposer device for use in testing a system-in-package device under test (DUT), the active thermal interposer device includes a body layer having a first surface and a second surface, wherein the first surface is operable to be disposed adjacent to a cold plate, and a plurality of heating zones defined across a second surface of the body layer, the plurality of heating zones operable to be controlled by a thermal controller to selectively heat and maintain respective temperatures thereof, the plurality of heating zones operable to heat a plurality of areas of the DUT when the second surface of the body layer is disposed adjacent to an interface surface of the DUT during testing of the DUT.

A coolant supplying apparatus, which is configured to prevent dew condensation from being generated in a supply of coolant, and a temperature controlling apparatus and a test handler including the same are provided. The coolant supplying apparatus includes a housing having an outlet, a coolant spraying part arranged inside the housing and configured to discharge coolant around the outlet of the housing, and a dry air injection part configured to inject dry air into the housing.