A method for instantaneous load pull impedance pattern generation uses a phase-frequency-location equivalent of the natural behavior of slide screw tuners to skew the reflection factor phase with only small frequency changes. The method is generic and applies the same to all GHz range test frequencies. A simple calculation determines the tuning probe position and the impedance cloud is generated quasi instantaneously by switching between sidebands of the carrier test frequency without mechanically moving the tuning probe. Benign frequency behavior of the tuners allows for simple and accurate narrowband interpolation. Duration of load pull measurements is reduced from minutes to seconds.

A testing apparatus for Devices Under Test (DUTs) includes at least one intake damper and at least one exhaust damper. At least one fan moves recirculated fluid and exterior fluid across one or more DUTs inside the testing apparatus. In one aspect, the testing apparatus includes a door to provide access to a chamber and the door includes at least one channel. At least a portion of the fluid flows through the at least one channel of the door. In another aspect, the door is configured to provide access to a chamber from the front of the chamber and the fluid is moved in a direction across the one or more DUTs substantially from the front of the chamber towards a rear of the chamber.

Described herein are systems, methods, and other techniques for identifying redundant parameters and reducing parameters for testing a device. A set of test values and limits for a set of parameters are received. A set of simulated test values for the set of parameters are determined based on one or more probabilistic representations for the set of parameters. The one or more probabilistic representations are constructed based on the set of test values. A set of cumulative probabilities of passing for the set of parameters are calculated based on the set of simulated test values and the limits. A reduced set of parameters are determined from the set of parameters based on the set of cumulative probabilities of passing. The reduced set of parameters are deployed for testing the device.

Systems and methods for semiconductor defect-guided burn-in and system level tests (SLT) are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an inline defect part average testing (I-PAT) subsystem, where the plurality of I-PAT scores is generated by the I-PAT subsystem based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a defectivity determined by the I-PAT subsystem based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more defect-guided dispositions for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.

A system and method for evaluating the reliability of semiconductor die packages are configured to sort a plurality of semiconductor dies with a Known Good Die (KGD) subsystem based on a comparison of an inline part average testing (I-PAT) score of each of the plurality of semiconductor dies to a plurality of I-PAT score thresholds, where the semiconductor die data includes the I-PAT score for each of the plurality of semiconductor dies, where the I-PAT score represents a weighted defectivity of the corresponding semiconductor die. The semiconductor dies may be filtered to remove at-risk semiconductor dies prior to sorting. The semiconductor die data may be received from a plurality of semiconductor die supplier subsystems. The KGD subsystem may transmit semiconductor die reliability data about the sorted plurality of semiconductor dies to a plurality of semiconductor die packager subsystems.

Examples of techniques for burn-in testing of an individually personalized device configuration are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: retrieving the individually personalized device configuration; enabling a device to receive the individually personalized device configuration, wherein the device is one of a plurality of devices; and loading the individually personalized device configuration to the device that is enabled, wherein other devices of the plurality of devices are disabled from receiving the individually personalized device configuration.

An integrated circuit method processes parametric data for each integrated circuit die in a plurality of integrated circuit die to determine an expected data pattern, screens integrated circuit die by comparing a data pattern corresponding to a plurality of parametric data for the integrated circuit die to an expected data pattern and, responsive to the comparing, determining whether a difference between the data pattern corresponding to a plurality of parametric data for the predetermined integrated circuit die and the expected data pattern is beyond a tolerance.

A computing system may include a shadow feature model training engine configured to access a set of integrated circuit (IC) layouts and capacitance values determined for components of the set of IC layouts. The shadow feature model training engine may construct shadow feature training data for the set of IC layouts, including by extracting shadow features for components of the set of IC layouts, combine extracted shadow features and determined capacitance values to form the shadow feature training data, and may further train a machine-learning (ML) model with the shadow feature training data. The computing system may also include a shadow feature application engine configured to extract shadow features for components of an input IC layout and determine capacitance values for the input IC layout via the trained ML model.

A cartridge, including a cartridge frame, formations on the cartridge frame for mounting the cartridge frame in a fixed position to an apparatus frame, a contactor support structure, a contactor interface on the contactor support structure, a plurality of terminals, held by the contactor support structure, for contacting contacts on a device, and a plurality of conductors, held by the contactor support structure, connecting the interface to the terminals.

A semiconductor inspection device includes: a measuring device that supplies power to a semiconductor device and measures the electrical characteristics of the semiconductor device; an optical scanning device that scans the semiconductor device with light intensity-modulated with a plurality of frequencies; a lock-in amplifier that acquires a characteristic signal indicating the electrical characteristics of the plurality of frequency components; and an inspection device that corrects a phase component of the characteristic signal at an arbitrary scanning position with a phase component at a scanning position reflecting the electrical characteristics of a first layer in the semiconductor device as a reference, specifies a phase component of the characteristic signal at a scanning position reflecting the electrical characteristics of a second layer, normalizes the phase component of the characteristic signal at the arbitrary scanning position by using the phase component, and outputs a result based on the normalized phase component.