Patent classifications
G01R31/2875
DIFFERENTIAL AGING MONITOR CIRCUITS AND TECHNIQUES FOR ASSESSING AGING EFFECTS IN SEMICONDUCTOR CIRCUITS
In some examples, this disclosure describes a method of operating a circuit. The method may comprise performing a circuit function under normal operating conditions, wherein performing the circuit function under the normal operating conditions includes performing at least a portion of the circuit functions via a characteristic circuit, performing at least the portion of the circuit function under enhanced stress conditions via a characteristic circuit replica, and predicting a potential future problem with the circuit function under the normal conditions based on an evaluation of operation of the characteristic circuit relative to operation of the characteristic circuit replica.
Integrated test cell using active thermal interposer (ATI) with parallel socket actuation
A testing apparatus comprises a test interface board comprising a plurality of socket interface boards, wherein each socket interface board comprises: a) an open socket to hold a DUT; b) a discrete active thermal interposer comprising thermal properties and operable to make thermal contact with the DUT; c) a superstructure operable to contain the discrete active thermal interposer; and d) an actuation mechanism operable to provide a contact force to bring the discrete active thermal interposer in contact with the DUT.
Wafer probe station
A wafer probe station includes a thermal chuck, a chuck stage, a platen, some probes, a first focusing device, a second focusing device and a thermal plate. The thermal chuck heats up to an operational temperature and holds a device under test (DUT). The chuck stage connects with the thermal chuck and moves the thermal chuck. The thermal chuck locates between the chuck stage and the platen. The probes are disposed on the platen and configured to contact with the DUT. The first focusing device is disposed on the platen to focus on the DUT. The second focusing device is disposed on the chuck stage to focus on the probes. The thermal plate locates between the second focusing device and the platen and is configured to heat up to the operational temperature. The thermal plate has a through hole aligning with the second focusing device.
Systems and methods for conforming test tooling to integrated circuit device with heater socket
A laminated heater socket useful in association with an integrated circuit (IC) device tester is having a socket with an embedded integrated heater. This laminated heater socket configuration allows for good thermal conductivity and better electrical signal transmission specially for testing high-speed integrated circuits.
THERMAL SENSOR
A method of calibrating a thermal sensor device is provided. The method includes extracting an incremental voltage to temperature curve for a diode array from a first incremental voltage of the diode array at a first temperature. The diode array and a device under test (DUT) which includes a thermal sensor are heated. After heating the diode array, a first incremental temperature is determined from the incremental voltage to temperature curve for the diode array and a second incremental voltage of the diode array after heating the diode array. An incremental voltage to temperature curve is extracted for the DUT from the first incremental temperature, a first incremental voltage for the DUT at the first temperature, and a second incremental voltage of the DUT after heating the device under test. A temperature error for the thermal sensor is determined from the incremental voltage to temperature curve for the DUT.
Compliant thermal contact device and method
Examples of thermal contact devices and methods are shown. Compliant thermal contact devices are shown that include interleaved conducting structures to provide a high thermal conduction contact area. Selected examples include a thermal interface material located at the interleaved interface between the conducting structures. Selected examples also include designs for alternate chip orientations.
Test chamber for memory device, test system for memory device having the same and method of testing memory devices using the same
A test system for a memory device includes: a chamber including at least one test socket column having a plurality of test sockets arranged in a first direction, wherein memory devices to be tested are in respective ones of the plurality of test sockets, a temperature adjusting apparatus configured to supply air into the chamber according to a temperature control signal to control a temperature of the chamber, a test device electrically connected to the test sockets and configured to test the memory devices, and a temperature controller configured to receive temperature information of the memory devices from temperature sensors of the memory devices and to output to the temperature adjusting apparatus the temperature control signal to compensate for a temperature difference between a detected temperature of the memory devices and a target temperature.
Control method of inspection apparatus and inspection apparatus
A control method of an inspection apparatus including a mounting stage on which a substrate having a plurality of inspection objects is mounted, a plurality of sections being formed with respect to the mounting stage and a heater controllable to heat for each of the sections includes when inspecting a first inspection object to be inspected among the plurality of inspection objects, causing the heater to heat a section corresponding to the first inspection object and a section corresponding to a second inspection object to be inspected next.
METHOD AND SYSTEM FOR PREDICTING HIGH-TEMPERATURE OPERATING LIFE OF SRAM DEVICES
A method for predicting high-temperature operating life of an integrated circuit (IC) includes performing bias temperature instability tests and high-temperature operating life tests on a device of the IC, establishing a relationship between the device bias temperature instability and the IC's high-temperature operating life based on a result of the bias temperature instability tests and the high-temperature operating life tests. The method further includes providing a lot of subsequent integrated circuits (ICs), performing wafer-level bias temperature instability tests on a device of the ICs, and predicting high-temperature operating life of the ICs based on a result of the wafer-level bias temperature instability tests and based on the established relationship between the device's bias temperature instability and the IC's high-temperature operating life. The method can save significant effort and time over conventional approaches for accurate prediction of high-temperature operating life of an IC.
THERMAL CONTROL OF A PROBE CARD ASSEMBLY
An example test system includes a test head and a probe card assembly connected to the test head. The probe card assembly includes: a probe card having electrical contacts, a stiffener connected to the probe card to impart rigidity to the probe card, and a heater to heat to at least part of the probe card assembly. A prober is configured to move a device under test (DUT) into contact with the electrical contacts of the probe card assembly.