A system for testing circuits of an integrated circuit semiconductor wafer includes a tester system for generating signals for input to the circuits and for processing output signals from the circuits for testing the wafer and a test stack coupled to the tester system. The test stack includes a wafer probe for contacting a first surface of the wafer and for probing individual circuits of the circuits of the wafer, a wafer thermal interposer (TI) layer operable to contact a second surface of the wafer and operable to selectively heat areas of the wafer, and a cold plate disposed under the wafer TI layer and operable to cool the wafer. The system further includes a thermal controller for selectively heating and maintaining temperatures of the areas of the wafer by controlling cooling of the cold plate and by controlling selective heating of the wafer TI layer.

A method for screening a semiconductor device for production of excessive random telegraph sequence (RTS) noise includes measuring noise of the semiconductor device at a first temperature, changing the temperature of the semiconductor device to a second temperature different from the first temperature, measuring noise of the semiconductor device at the second temperature, extracting a characteristic of the measured noise at the first and second temperatures (e.g., standard deviation, HMM output, frequency domain spectrum of time domain noise measurement), making a comparison of the extracted first and second noise characteristics, and making a determination whether the semiconductor device produces excessive RTS noise based on whether the comparison is above a predetermined threshold. Two different bias conditions of the device may be employed rather than, or in addition to, the two different temperatures.

A testing apparatus comprises a test interface board comprising a plurality of socket interface boards, wherein each socket interface board comprises: a) an open socket to hold a DUT; b) a discrete active thermal interposer comprising thermal properties and operable to make thermal contact with the DUT; c) a superstructure operable to contain the discrete active thermal interposer; and d) an actuation mechanism operable to provide a contact force to bring the discrete active thermal interposer in contact with the DUT.

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

A test system for a memory device includes: a chamber including at least one test socket column having a plurality of test sockets arranged in a first direction, wherein memory devices to be tested are in respective ones of the plurality of test sockets, a temperature adjusting apparatus configured to supply air into the chamber according to a temperature control signal to control a temperature of the chamber, a test device electrically connected to the test sockets and configured to test the memory devices, and a temperature controller configured to receive temperature information of the memory devices from temperature sensors of the memory devices and to output to the temperature adjusting apparatus the temperature control signal to compensate for a temperature difference between a detected temperature of the memory devices and a target temperature.

A test wafer according to an embodiment of the present disclosure is a test wafer used for simulation of heat emission of devices on a wafer, and includes a silicon wafer and a silicon heater bonded to a surface of the silicon wafer.

A dual loop type temperature control module and an electronic device testing apparatus having the same are provided. The temperature control module comprises a first loop through which a first working fluid of a first temperature flows, a second loop through which a second working fluid of a second temperature flows, a controller for controlling a first switching valve such that the first or second working fluid flows through a temperature regulating device, and a second switching valve such that the working fluid flowing through the temperature regulating device returns to the first or second loop. The temperature regulating device adjusts a thermoelectric cooling device to reach two different reference temperatures based on the rise/fall of its temperature dependent on the working fluid. The thermoelectric cooling device regulates the temperature of the tested object under a wide range of temperature difference and with accuracy based on the reference temperatures to facilitate the detection of high/low temperature.

A testing environment may have at least one controller connected to at least first and second testing slots positioned in a housing. The first testing slot can be configured with a first thermal range capability and the second testing slot may be configured with a second thermal range capability that differs from the first thermal range capability.

A testing system includes: an inspection module including a plurality of levels of inspection chambers in each of which a tester part having a tester configured to perform an electrical inspection of an inspection object and a probe card is accommodated; an aligner module configured to align the inspection object with the tester part; an alignment area in which the aligner module is accommodated; and a loader part configured to load the inspection object into the alignment area and unload the inspection object out of the aligner module, wherein the inspection module is located adjacent to the alignment area.

A thermal test head for an integrated circuit device includes a heat exchanger assembly, a contact assembly configured to contact the integrated circuit, and a thermal control assembly disposed between the heat exchanger assembly and the contact assembly. The thermal control assembly includes a Peltier device in thermal contact with opposing surfaces of the heat exchanger assembly and the contact assembly, and a spacer in physical contact with the opposing surfaces of the heat exchanger assembly and the contact assembly.