A method, system and computer program product, the method comprising: obtaining circuit information, comprising description of groups of pins of electronic chips; obtaining a description of a test comprising a plurality of rules specifying: an identifier, a first group of pins, a second group of pins, a first action to take upon successful interconnection of the first and second groups, and a second action to take upon failure, wherein the first action and second actions are one of: finish with success, finish with failure, and a rule ID of a subsequent rule to check; checking the plurality of rules, comprising checking a sequence of rules starting with a first rule, and wherein each subsequent rule is selected as the first or second action of a preceding rule, in accordance with whether the preceding rule succeeded or failed, respectively; and outputting a result of the plurality of rules.

A system for verifying signals in electronic circuits that includes a waveform translator and a test-and-measurement instrument. The waveform translator is configured to receive a simulated waveform for a node of a simulated prototype circuit and to translate the simulated waveform into a translated waveform. The test-and-measurement instrument is configured to obtain a measured waveform and to determine a deviation of the measured waveform from the simulated waveform using the translated waveform.

A system and method of detecting defects in an analog circuit is provided. A method includes identifying a channel connected block (CCB) from a netlist, creating defect for the CCB to be injected during a simulation, obtaining a first measurement of an output node of the CCB by performing a first analog circuit simulation for the CCB based on providing excitations as inputs to the CCB and obtaining a second measurement of the output node of the CCB by performing a second analog circuit simulation for the CCB based on providing the excitations as the inputs to the CCB and injecting the defect. The method can further include determining a defect type based on the first measurement and the second measurement.

An example system includes a processor to receive a template-aware coverage data that tracks probabilities of events in a list of events being hit for a set of test-templates over a first and second predetermined period of time. The processor is to generate a hit prediction score for each combination of unhit event in the events and each test-template in the set of test-templates of the second predetermined period of time. The hit prediction score indicates a probability of an unhit event being hit by a particular test-template in a future third predetermined period of time based on the template-aware coverage data and similarities between the events and the test-templates. The processor is to generate a template score for each test-template based on the hit prediction scores for each test-template. The processor is to select a test-template from the set of test-templates based on the template score.

The methods and systems are directed to automated computer analysis and machine learning. Specifically, the systems and methods for using machine learning to generate fault prediction models and applying the fault prediction models to logical circuits to optimize test point insertion determinations and optimize fault detection in the logical circuit. Disclosed are methods and systems that that generates training data from training circuits (and optionally generate training circuits), trains a learning segment (which may include an artificial neural network (ANN)) using the training data. The learning segment (once trained) generates fault prediction models to predict the quality of a TP inserted on a given circuit location and optimize TPI for a given circuit. The methods and systems described provide computational (CPU/processing) time advantages and precision over conventional methods.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a touchless testing platform employed to, for example, create automated testing scripts, sequence test cases, and implement defect solutions. In one aspect, a method includes receiving a log file and testing results generated from a code base for an application; processing the log file through a pattern-mining algorithm to determine a usage pattern of code modules within the code base; clustering defects from the testing results based on a respective functionality of the application reported within each of the defects; generating testing prioritizations for test cases for the application by assigning weightages to the test cases based on the clusters of defects and the usage pattern of the code modules within the code base; sequencing a set of the test cases based on the test prioritizations; and transmitting the sequence to a test execution engine.

A series of pseudo-random test patterns provide inputs to a logic circuit for performing logic built-in self test (LBIST). A weight configuration module applies one or more weight sets to the pseudo-random test patterns, to generate a series of weighted pseudo-random test patterns. A logic analyzer determines a probability expression for each given net of the logic circuit, based on associated weight sets and a logic function performed by the net. A probability module computes an output probability for each net based on associated probability expressions and associated input probabilities. The weight configuration module optimizes the weight sets, based on the computed net probabilities, and further based on a target probability range bounded by lower and upper cutoff probabilities.

A method is provided for testing the functionality of a device under test interface circuitry located between automated testing equipment (ATE) and a device under test (DUT). The method includes disconnecting the device under test from the device under test interface circuitry, utilizing a Source Measurement Unit (SMU) that generates and measures voltage and current and uses force and sense lines, and testing a switch located in the device under test interface circuitry using a two-state alarm process. The method also includes applying a voltage using the a voltage source measurement device in a first state in which force and sense lines of the voltage source measurement device are connected in the device under test interface circuitry. The method further includes detecting whether an alarm signal due to an open circuit has been activated, and determining that the switch being tested in the device under test interface circuitry is operating properly by the absence of the alarm signal being activated.

A model is generated for predicting failures at the wafer production level. Input data from sensors is stored as an initial dataset, then data exhibiting excursions or useless impact is removed from the dataset. The dataset is converted into target features, where the target features are useful in predicting whether a wafer will be normal or not. A trade-off between positive and negative results is selected, and a plurality of predictive models are created. The final model is selected based on the trade-off criteria, and deployed.

A series of pseudo-random test patterns provide inputs to a logic circuit for performing logic built-in self test (LBIST). A weight configuration module applies one or more weight sets to the pseudo-random test patterns, to generate a series of weighted pseudo-random test patterns. A logic analyzer determines a probability expression for each given net of the logic circuit, based on associated weight sets and a logic function performed by the net. A probability module computes an output probability for each net based on associated probability expressions and associated input probabilities. The weight configuration module optimizes the weight sets, based on the computed net probabilities, and further based on a target probability range bounded by lower and upper cutoff probabilities.