Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a touchless testing platform employed to, for example, create automated testing scripts, sequence test cases, and implement determine defect solutions. In one aspect, a method includes the actions of receiving requirements documentation for an application through a user interface (UI), analyzing the requirements documentation to extract terminologies based on an entity term corpus; categorizing the extracted terminologies based on a corpus of known terms; generating a semantic graph from standardized statements constructed from the categorized extracted terminologies; generating a process flow map for the application by identifying processes of the application and a respective relationship between each process from the semantic graph; generating a test scenario map of test scenarios for the application from the process flow map and the semantic graph; and providing the test scenario map to a tester through the UI.

Constant-output-value gates and buffer gates are determined for gates in a circuit design based on a hold-toggle pattern. The hold-toggle pattern determines in which shift clock cycles in a segment of consecutive shift clock cycles one or more scan chains receive bits based on corresponding bits of a test pattern or same bits as bits of previous shift clock cycles during a shift operation. Activation probabilities and observation probabilities are then determined for circuit nodes of the circuit design based at least in part on the constant-output-value gates and the buffer gates. Finally, test patterns are generated based on the activation probabilities and the observation probabilities.

A method including determining, for a given hardware link, whether a signal error rate for signals sent over the given hardware link is beyond a given threshold, when the signal error rate is beyond the given threshold, generating an error indication for the given hardware link, the error indication including a prediction that a hardware component associated with the given hardware link is likely to fail. Related apparatus and methods are also provided.

This disclosure includes systems, methods, and techniques for controlling a plurality of light-emitting diodes (LEDs). For example, a circuit includes a switching device, where the switching device is electrically connected to an LED of the plurality of LEDs, and where the switching device is configured to control whether the LED receives an electrical signal from a power source. Additionally, the circuit includes processing circuitry configured to determine that the LED is associated with a bright failure condition by attempting to prevent the LED from receiving the electrical signal from the power source using the switching device and disable the LED in response to detecting the bright failure condition.

The system and method of using a debug interface recorder and replay unit for debugging and testing devices of interest such as integrated circuits by using a debug interface buffer controller to receive, record, and replay sequences of instructions to the integrated circuit. This is particularly useful for deployed devices that are difficult or dangerous to access. This is also beneficial for devices that cannot be reached (e.g., after launch). By recording sequences and storing them for later use, and by communicating commands and configuration settings to a device, system maintenance and troubleshooting is accomplished saving valuable time and money without requiring physical access to the device of interest.

A digital circuit robustness verification method is provided that includes the following steps. An internal storage circuit and an external storage circuit corresponding to a circuit under test are set to store a plurality of random values and a configuration of the circuit under test for performing a predetermined function is set by a processing circuit. A driving signal corresponding to the predetermined function is transmitted to the circuit under test by a previous stage circuit, such that the circuit under test executes the predetermined function to further generate an output signal. The determination as to whether the output signal is correct or not is made by a next stage circuit, and the circuit under test is determined to pass a robustness verification when the output signal is correct.

A method including determining, for a given hardware link, whether a signal error rate for signals sent over the given hardware link is beyond a given threshold, when the signal error rate is beyond the given threshold, generating an error indication for the given hardware link, the error indication including a prediction that a hardware component associated with the given hardware link is likely to fail. Related apparatus and methods are also provided.

Techniques for implementing and using failure curve analytics in an equipment maintenance system are disclosed. A method comprises: accessing a failure curve model for an equipment model, the failure curve model being configured to estimate lifetime failure data for the equipment model for different failure modes corresponding to different specific manners in which the equipment model is capable of failing, the lifetime failure data indicating a probability of the equipment model failing in the specific manner of the failure mode; generating first analytical data for a first failure mode of the plurality of failure modes using the failure curve model based on the first failure mode, the first analytical data indicating at least a portion of the lifetime failure data for the equipment model corresponding to the first failure mode; and causing a visualization of the first analytical data to be displayed on a computing device.

A system and method for providing convergence centric coverage for clock domain crossing (CDC) jitter in simulation is described. The method includes, in part, defining one or more design constraints associated with the circuit design, determining at least one group of converging signals associated with the circuit design using the one or more design constraints, applying a multitude of jitters to clock domain crossing (CDC) paths of the at least one group of converging signals, and storing the jitters in a jitter database.

Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for in-field safety tests on system-level and circuit-level, providing real-time and on-chip tests with respect to, including but not limited to, circuit reliability, power consumption, and system safety. The in-field safety tests may include implementing voltage droop monitors (VDMs) and signature collectors with authentication-enabled launching. Other embodiments may be described and claimed.