A method or system for estimating delays in design under tests (DUTs) using machine learning. The system accesses multiple DUTs, each comprising various logic blocks. For each DUT, a combinatorial path is identified, connecting one or more logic blocks. A feature vector is generated, including values of orthogonal features representing the combinatorial path's characteristics. Each DUT is compiled for emulation, and the delay of its combinatorial path is measured. These measured delays, along with the corresponding feature vectors, are used to train a machine learning delay model. The trained model is designed to receive a combinatorial path of a DUT as input and generate an estimated wire delay as output. This approach leverages machine learning to predict delays in electronic designs, improving the efficiency and accuracy of delay estimations in complex circuits.

A simulation method and system of verifying an operation of a semiconductor memory device of a memory module at a design level. The simulation method includes setting a configuration and an arrangement of a registered clock driver (RCD) and a configuration and an arrangement of first semiconductor memory devices to fourth semiconductor memory devices, on a printed circuit board (PCB) through a graphic user interface (GUI). When a RCD test execution command is applied through the GUI, executing a test program to apply control signals to control signal terminals of the PCB based on a command truth table, to compare the applied control signals and control signals output through first driver output terminals of the RCD, and to create an RCD test result. When the RCD operates normally, performing a test on the memory module.

An electronic device test database generating method, comprising: (a) acquiring cell layout information of a target electronic device; (b) generating possible defect location information of the target electronic device according to the cell layout information, wherein the possible defect location information comprises at least one possible defect location of the target electronic device; (c) testing the target electronic device according to the possible defect location information to generate a testing result; and (d) generating an electronic device test database according to the testing result.

Thermal conditions can be simulated for an electronic device. Application developers may want to test how applications perform under various thermal conditions on a device that includes thermal management. The application developers can use the tests to determine whether the application should take proactive measures to maintain application performance, and which proactive measures should be taken. For example, an application can reduce its use of resources to ensure that an application maintains a desired quality of user experience (and at a minimum remains responsive) under adverse thermal conditions. Creating adverse conditions can be difficult to replicate, costly to implement, and can potential cause damage to the electronic device being tested. In some examples, simulating thermal conditions can be used instead of placing the device in real-world adverse conditions to improve the testing process for developers.

Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by replacing one or more of the data transformation elements in the hardware design with a function element which is treated as an unevaluated function of its combinational inputs by a formal verification tool such that during formal verification the function element will produce the same output for the same inputs, and formally verifying that for each transaction of a set of transactions an instantiation of the modified hardware design for the data transformation pipeline produces a set of one or more outputs that matches a reference set of one or more outputs for that transaction.

Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by formally verifying that the output of an instantiation of the hardware design produces the same output as an instantiation of a hardware design for another data transformation pipeline for a predetermined set of transactions under a constraint that substantially equivalent data transformation elements between the data transformation pipelines produce the same output(s) in response to the same input(s).

A prediction system predicts compatibility of an existing test and measurement setup with a potential extension unit based on digital signatures. The prediction system includes a receiving unit, a processing unit, and a display unit. The receiving unit is configured to receive a digital signature from the potential extension unit and to forward the digital signature to the processing unit. The processing unit is configured to process the digital signature in order to predict whether the existing test and measurement setup is compatible with the potential extension unit. The processing unit is further configured to forward the result of the prediction to the display unit so that the result of the prediction is displayed. In addition, a method for predicting compatibility of an existing test and measurement setup with a potential extension unit based on digital signatures is described.

A method for evaluating tests for fabricated integrated circuit (IC) chips includes providing, design for fault injection (DfFI) instances of an IC design that characterize activatable states of controllable elements in an IC chip based on the IC design. The method also includes fault simulating the IC design a corresponding identified test suite to determine a signature for faults and simulating the IC design with the DfFI instances activated to determine a signature for the DfFI instances. The method includes generating a DfFI-fault equivalence dictionary based on a comparison of the signature of the faults and DfFI instances and generating tests for a fabricated IC chip based on the IC design. The method includes receiving test result data characterizing the tests being applied against the fabricated IC chip with the DfFI instances activated and analyzing the test result data to determine an ability of the tests to detect the faults.

A method for verifying an integrated circuit (IC) design described in a hardware description or hardware verification language (HDHVL) is provided. The method includes identifying connections between random variables and coverage areas of the IC design, as described in HDHVL code, the connections being identified by determining which coverage areas of the IC design will be influenced during simulation by which random variables. The method can further include storing the identified connections in a database, and using, by a processor, connections retrieved from the database to simulate and verify the coverage areas of the IC design.

The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, an electronic design and linking a printed circuit board (PCB) block to a physical layout associated with the electronic design. Embodiments may further include receiving, at a layout environment, at least one simulation parameter and performing, using a finite difference time domain (FDTD) simulator, a time-domain simulation, based upon, at least in part, the at least one simulation parameter.