Aspects include parsing, by a computer system, a design file of an integrated circuit including a plurality of stages to extract a plurality of inputs and outputs of a plurality of latches. The computer system can sort the latches based on latch locations in the stages and build a plurality of ordered vectors of signals before and after the latches based on the sorting. The computer system can build a plurality of parity vectors for each of the ordered vectors of signals before and after the latches, build a latch bank for each of the parity vectors before the latches, and build a parity vector comparison to detect a parity failure based on comparing the parity vectors after the latches with an output of the latch bank.

A semiconductor device of an embodiment includes a main circuit, a monitoring circuit, a comparator, and a DFT control circuit. The monitoring circuit includes a same circuit configuration as a circuit configuration of the main circuit. The comparator compares an output of the main circuit and an output of the monitoring circuit. The DFT control circuit inverts a value of at least one flipflop, among values of a plurality of flipflops provided in the main circuit, and sets the inverted value to at least one flipflop via a scan chain.

A camouflaged shift registers and method for producing same is disclosed. In one embodiment, the camouflaged shift register comprises a plurality of serially coupled flip-flops, each of the flip-flops comprising a logic output communicatively coupled to an input of a serially adjacent next flip-flop and a camouflage element communicatively coupled between the logic output of a first flip-flop of the plurality of flip-flops and the input of a second flip-flop of the plurality of flip-flops serially adjacent to the first flip-flop, wherein the camouflage element has a physical layout mimicking a first function but performs a second function different from the first function.

The present disclosure generally relates to semiconductor structures and, more particularly, to measurement circuits for logic paths and methods of manufacture. The circuit includes: a flip flop device outputting an output signal comprising an intrinsic delay; a logic path looping the output signal back to the flip flop device such that the intrinsic delay is to be received by the flip flop device; and an oscillator which feeds an input signal into the logic path and sweeps the input signal to alter the looped output signal thereby providing a maximum frequency of the logic path.

A non-transitory computer-readable recording medium stores a test pattern generation program for causing a computer to execute processing including: detecting, based on design information of a semiconductor integrated circuit, a plurality of clock domains each of which operates according to any one of a plurality of clock signals; changing application order of the plurality of clock signals when a test pattern that includes the application order and a first input value to a first object circuit is generated, based on which of the plurality of clock domains a first holding circuit that sends the first input value or a first response value from the first object circuit to the first circuit region and a second holding circuit that receives the first response value from the first circuit region, belong to; and outputting information regarding the test pattern.

Methods and systems for on-die measuring jitter of a clock under test are presented. In an aspect, an apparatus comprises a delay line having a plurality of delay elements, the outputs of which are sampled at the expected transition time of the clock under test. The sampled outputs are provided to an edge detector that indicates the presence of the clock transition at a specific time, and a latching circuit stores a record of all the edge locations seen during a sampling window. In some aspects, a counting circuit counts and stores how many times the transition occurs at each specific time during the sampling window. The counts stored by the counting circuit provide histogram data that can be analyzed to determine the jitter characteristics of the clock under test.

Implementations described herein relate to a core and interface scan testing. In some implementations, an integrated circuit may include input scan flip-flops (ISFFs) arranged in multiple ISFF stages that include a first ISFF stage and a second ISFF stage. Inputs to the first ISFF stage are connected to inputs of the integrated circuit. Inputs to the second ISFF stage are connected to outputs of a logic component that is connected to outputs of the first ISFF stage. The integrated circuit may include output scan flip-flops (OSFFS) arranged in multiple OSFF stages that include a first OSFF stage and a second OSFF stage. Outputs from the first OSFF stage are connected to outputs of the integrated circuit. Outputs from the second OSFF stage are connected to inputs of a logic component that is connected to inputs of the first OSFF stage. The integrated circuit may include core scan flip flops.

A scan flip-flop circuit includes a selection circuit including first and second input terminals coupled to first and second I/O nodes, a flip-flop circuit coupled to the selection circuit, a first driver coupled between the flip-flop circuit and the first I/O node, and a second driver coupled between the flip-flop circuit and the second I/O node. The selection circuit and drivers receive a scan direction signal. In response to a first logic level of the scan direction signal, the selection circuit responds to a first signal received at the first input terminal, and the second driver outputs a second signal responsive to a flip-flop circuit output signal. In response to a second logic level of the scan direction signal, the selection circuit responds to a third signal received at the second input terminal, and the first driver outputs a fourth signal responsive to the flip-flop circuit output signal.

Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.

A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.