A multi-bit flip-flop includes: a single scan input pin to receive a scan input signal, a plurality of data input pins to receive first and second data input signals, a first scan flip-flop to select one of the scan input signal and the first data input signal as a first selection signal in response to a scan enable signal and to latch the first selection signal to provide a first output signal, a second scan flip-flop to select one of an internal signal corresponding to the first output signal and the second data input signal as a second selection signal in response to the scan enable signal and to latch the second selection signal to provide a second output signal, and a plurality of output pins to output the first and second output signals, wherein scan paths of the first and second scan flip-flops are connected to each other.

Disclosed is a semiconductor integrated circuit including a logic circuit, and a plurality of scan flip-flop circuits that hold input data or output data of the logic circuit and are capable of forming a scan chain for executing a scan test of the logic circuit. Each scan flip-flop circuit includes a scan data input part that receives input of scan data for the scan test, a normal data input part that receives input of normal data different from the scan data, and a data holding part capable of separately holding the normal data and the scan data.

A failing latch is identified on a chip including a plurality of latches with the failing latch receiving data propagated from a first set of test input latches. A diagnostic set of latches is determined which includes the failing latch and a set of related latches. The set of related latches each receives data propagated from at least one test input latch from the first set of test input latches. The set of related latches is identified from a related latches table. One or more tests are performed on the chip and test output data is collected from the diagnostic set of latches. The related latches table is created by tracing from a target latch.

Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

A semiconductor device includes a scan input circuit, a master latch, a slave latch, a first inverter, and a scan output circuit. The scan input circuit is configured to receive a scan input signal, a first data signal, and a scan enable signal and select any one of the first data signal and the scan input signal in response to the scan enable signal to output a first select signal. The master latch is configured to latch the first select signal and output a first output signal. The slave latch is configured to latch the first output signal and output a second output signal. The first inverter is configured to invert the second output signal. The scan output circuit is configured to receive a signal output from the slave latch and an external signal and output a first scan output signal.

A flip flop circuit includes a first master portion, a second master portion, at least one determining portion and a slave portion. The first master portion is configured to operate at a first mode and to receive a first input and generate first master outputs. The second master portion is configured to operate at a second mode and to receive a second input and generate second master outputs. The at least one determining portion is configured to receive at least one enable signal, and has determining inputs and determining outputs. The determining inputs are connected to the first master outputs and the second master outputs. The determining portion is configured to determine the determining outputs being the first master outputs or the second master outputs according to the at least one enable signal. The slave portion is configured to receive the determining outputs and generate an output signal.

An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between the top surface and the bottom surface. A through silicon via (TSV) has a conductive body in the opening, has a top contact point coupled to the body at the top surface, and has a bottom contact point coupled to the body at the bottom surface. A scan cell has a serial input, a serial output, control inputs, a voltage reference input, a response input coupled to one of the contact points, and a stimulus output coupled to the other one of the contact points.

An unbalanced multiplexer and a scan flip-flop including the unbalanced multiplexer, wherein the unbalanced multiplexer includes a first transmission circuit transmitting a first input signal to an output terminal according to a logic state of a selection signal; and a second transmission circuit transmitting a second input signal to the output terminal according to the logic state of the selection signal. A delay characteristic of a first transmission path from a first input terminal to the output terminal along which the first input signal of the first transmission circuit is transmitted, and a delay characteristic of a second transmission path from a second input terminal to the output terminal along which the second input signal of the second transmission circuit is transmitted, are set differently.

Aspects include techniques for bypassing an encoded latch on a chip during a test-pattern scan and using on-chip circuitry to generate a desired encoded pattern, which is inserted into a scan-bypassed latch, to test the on-chip circuitry for defects. A computer-implemented method may include applying a global control bit to the chip; initializing a scan of the chip while bypassing the encoded latch; and applying an extra scan clock to initiate the encoded latch after completing the scan, wherein the encoded latch is updated with check bits generated by the on-chip circuitry.

A data storage apparatus is provided which has a plurality of data storage units, each respective data storage unit configured to store a respective data bit of a data word. Stored data value parity generation circuitry is configured to generate a parity bit for the data word in dependence on the data bits of the data word stored in the plurality of data storage units. The stored data value parity generation circuitry is configured such that switching within the stored data value parity generation circuitry does not occur when the data word is read out from the plurality of data storage units. Transition detection circuitry is configured to detect a change in value of the parity bit.