The disclosure relates to a scan chain circuit comprising cascaded flip-flops having a functional input node and a test input node configured to be selectively coupled to logic circuitry at a clock edge time. A clock line is provided configured to distribute one or more clock signals to the flip-flops in the chain, wherein the flip-flops in the chain have active clock edges applied thereto at respective clock edge times. The chain of flip-flops comprise a set of flip-flops configured to receive an edge inversion signal and to selectively invert their active clock edges in response to the edge inversion signal being asserted.

An Integrated Circuit (IC) includes a storage element and control circuitry. The control circuitry is configured to select, responsively to a scan-enable control, between a functional-data input and a scan-data input to serve as an input to the storage element, to selectively disable toggling of an output of the storage element, responsively to a clock-enable control, by gating a clock signal provided to the storage element, and, while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, to select the input of the storage element to be the scan-data input.

A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

A circuit, including a TAP circuit, a routing circuit, a first test path and a second test path, is provided. A first input terminal and a first output terminal of the routing circuit are respectively coupled to a scan output terminal and a first scan input terminal of the TAP circuit. A first terminal of the first test path is coupled to a second input terminal of the routing circuit. A second terminal of the first test path is coupled to a second output terminal of the routing circuit. A first terminal of the second test path is coupled to a third input terminal of the routing circuit. A second terminal of the second test path is coupled to a third output terminal of the routing circuit. The routing circuit couples the scan output terminal of the TAP circuit to the first scan input terminal of the TAP circuit or the first terminal of the first test path or the first terminal of the second test path.

According to one embodiment, a semiconductor device includes a control circuit configured to generate a first signal and a second signal, a gating circuit configured to execute supply or stoppage of supply of a clock signal based on the first signal, and a circuit block configured to accept the clock signal, the second signal, and a test pattern. The gating circuit is configured to execute resupply of the clock signal after the stoppage of the supply, based on the first signal during a period of a scan test.

A circuit, including a TAP circuit, a routing circuit, a first test path and a second test path, is provided. A first input terminal and a first output terminal of the routing circuit are respectively coupled to a scan output terminal and a first scan input terminal of the TAP circuit. A first terminal of the first test path is coupled to a second input terminal of the routing circuit. A second terminal of the first test path is coupled to a second output terminal of the routing circuit. A first terminal of the second test path is coupled to a third input terminal of the routing circuit. A second terminal of the second test path is coupled to a third output terminal of the routing circuit. The routing circuit couples the scan output terminal of the TAP circuit to the first scan input terminal of the TAP circuit or the first terminal of the first test path or the first terminal of the second test path.

The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

Sensor data relating to operating conditions for an integrated circuit are read out through scan chains. Scan tests are run on an integrated circuit containing logic circuits that implement logic functions. The logic circuits are interconnected to form scan chains which are used in running the scan tests. The scan test data resulting from the scan tests is read out from the logic circuits through these scan chains. During the scan tests, sensor blocks capture measurements of the operating conditions for the logic circuits. The operating conditions may include process, voltage and/or temperature conditions, for example. The sensor blocks are also interconnected to form one or more scan chains, and sensor data produced from the captured measurements is read out through these scan chains concurrently with the read out of the scan test data.