A Switching Mode Interposer (SMI) arrangement for boundary-scan testing of a Multi-Chip Module having a System-On-Chip, a Microprocessor Control Unit, and multiple chiplets-based devices including central processing units, graphical processing units, and/or memory devices disposed on a two-tiered interposer-substrate system. The SMI includes (a) a twin Test Access Port connected to a JTAG controller and configured to transmit test data in one direction (TAP-X) and an opposite direction (TAP-Y) along an Inter-Integrated Circuit (I2C) bus connected with the SOC, the MCU and the multiple devices, the test data being formatted according to IEEE 1149.1 or IEEE 1149.7 standard; and (b) a Mux/DeMux switch connected to the twin TAP and the I2C bus and responsive to the SOC or the MCU for selective switching of the test data along either the TAP-X or TAP-Y direction to a predetermined port associated with one of the multiple devices.

A test access port circuit includes a data input terminal, a reset terminal, a mode selection terminal, at least one test data register set, an auxiliary data register set, an instruction register set, and a controller. The controller is coupled to the mode selection terminal and the instruction register set, and controls the at least one test data register set, the auxiliary data register set, and the instruction register set according to at least mode selection signal received by the mode selection terminal. In a reset terminal input mode, when the controller controls a test data register set of the at least one test data register set to store a first input data bit received by the data input terminal, the auxiliary data register set stores a second input data bit received by the reset terminal.

A clock gating cell (CGC) is provided. The clock gating cell includes two latches that can be configured as a flip-flop to use positive/negative edges of a first clock signal to store a value of an input terminal, and the clock gating cell also includes a selector used for the flip-flop to select from values of different input terminals for storing. In addition, in a non-scan testing mode, the clock gating cell can forcefully close an unused latch through an independent signal, and in a scan shift duration and a scan capture duration of a scan testing mode, the clock gating cell can further forcefully output the first clock signal as the gating clock signal according to two independent signals.

A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.

Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.

A combinational circuit block has input pins configured to receive input digital signals and output pins configured to provide output digital signals as a function of the input digital signals received. A test input pin receives a test input signal. A test output pin provides a test output signal as a function of the test input signal received. A set of scan registers are selectively coupled to either the combinational circuit block or to one another so as to form a scan chain of scan registers serially coupled between the test input pin and the test output pin. The scan registers in the set of scan registers are clocked by a clock signal. At least one input register is coupled between the test input pin and a first scan register of the scan chain. The at least one input register is clocked by an inverted replica of the clock signal.

A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.

A circuit comprises a clock gating device. The clock gating device comprises a multiplexing device and circuitry for generating multiplexer input signals. The selector input of the multiplexing device is coupled to a clock signal. The multiplexing device selects the first input signal to send to an output of the multiplexing device when the selector input is set to “0” and selects the second input signal to send to the output of the multiplexing device outputted when the selector input is set to “1”. The circuitry for generating multiplexer input signals is configured to ensure the timing of the transitions on the output are derived from the timing of the transitions of the clock signal and not by the timing of the transition of the first and second inputs of the multiplexing device.

According to one general aspect, an apparatus may include a first power signal having a high voltage. The apparatus may include a second power signal having a low voltage. The apparatus may include a third power signal having a voltage configured to switch between the high voltage and the low voltage. The apparatus may include a latching circuit powered by the first power signal and the second power signal. The apparatus may include a selection circuit configured to select between, at least, a first data signal and a second data signal, and powered by the first power signal, the second power signal, and the third power signal.

A semiconductor integrated circuit includes: scan chains each of which includes a serial connection of sequential circuits and performs a shift register operation in a scan test; and an ICG chain composed by coupling, to one another, ICG circuits each of which individually supplies any of the scan chains with a circuit clock signal for operating the sequential circuits. In the ICG chain, an ICG enable propagation signal for controlling timing when the ICG circuits output the circuit clock signals propagates through a signal line and is input sequentially to the ICG circuits. The ICG circuits output the circuit clock signals at pieces of timing which are different between the scan chains.