A reconfigurable JTAG includes, in part, a core logic, a boundary scan chain cell, one or more reconfigurable blocks (RBs), and a reconfigurable block (RB) programming module. The RBs may include, in part, one or more reconfigurable boundary scan chain blocks (RBB) adapted to couple the boundary scan chain cell to the core logic and to input/output (I/O) ports of the reconfigurable JTAG. The RBs may also include, in part, one or more additional reconfigurable logic (ARL) blocks to provide enhanced logic for locking operations. The RB programmable module may communicate with a memory storing data for configuring the RBBs and ARLs. The RB programming module may configure the RBBs and ARLs based at least in part on the data stored in the memory to disable access to the I/O ports of the JTAG. The RB programming module may configure the RBBs to encrypt the I/O ports in accordance with a cipher algorithm. The RB programming module may also configure the RBBs and ARLs to compare a counter's count to a predefined time and lock the I/O ports after an expiration of the predefined time.

An extended joint test action group based controller and a method of use allows easier testing of integrated circuits by reducing the power dissipation of an IC. The extended joint test action group (JTAG) controller tests internal storage elements that form digital units in an integrated circuit (IC) use a design for testing scan infrastructure on the IC, wherein the JTAG controller is extended by an overall reset generator for all digital units of the IC, and a finite state machine controls the overall reset generator. In reset mode the JTAG controller stops the at least one clock module in supplying the digital units that should be reset. It then sets all scan chains in test mode and switches the input multiplexers into reset mode; and then controls the number of shift clock cycles for shifting in the reset value to the flip-flops in the scan chain, respectively.

An integrated circuit and an electronic device including the integrated circuit are provided. An integrated circuit includes a sequential logic circuit, which includes a first scan cell that is configured to receive a scan input, and a plurality of scan cells sequentially connected in series from the first scan cell, a control unit, which is configured to receive a selection signal including an output of each of the plurality of scan cells, and is further configured to output a control signal responsive to the selection signal, and a monitoring circuit, which is configured to receive the control signal, is configured to perform first monitoring of first data at a first node that is an observation node in the sequential logic circuit responsive to the control signal, and is configured to output a result of the first monitoring to a monitoring node.

A semiconductor integrated circuit to receive a test scan input, a test clock, and a test mode signal and output a secure scan output signal, the integrated circuit including: a secure key circuit to generate delay input signals, which are differently delayed from the test scan input, and to generate an input key signal by capturing the delay input signals in response to the test clock; a key comparator to generate a verification result indicating whether an input key of the input key signal is identical with a preset reference key; a chip to generate a scan output signal based on the test scan input; a scan output remapper to obfuscate the scan output signal according to the verification result and to output the obfuscated scan output signal as the secure scan output signal; and a secure scan controller to control the secure key circuit, key comparator, chip, and remapper.

A processor comprises an exchange, a plurality of columns, and a plurality of exchange scan chains. The exchange comprises a plurality of exchange paths, each comprising a set of exchange path portions, for transmitting data between processing units. Each of the plurality of column comprises processing units, each processing unit connected to output data to a respective exchange path, and column pipe circuitry for providing a controllable path between the exchange and the processing units. The column pipe circuitry comprises a column wrapper chain for preventing a scan test signal from passing between the exchange paths and the processing units. The exchange scan chains enable scan testing of the exchange paths. Each exchange scan chain comprises a plurality of scan chain segments, each scan chain segment comprises an exchange path portion connected to at least one of the processing units of at least one of the columns of the processor.

A circuit comprises a plurality of clock control devices. Each of the clock control devices is configured to generate a scan test clock signal for a particular clock domain in the circuit and comprises circuitry configured to select clock pulses of a fast clock signal as scan capture clock pulses for the particular clock domain based on a particular clock pulse of a slow clock signal and a scan enable signal. The order and spacing between the groups of the scan capture clock pulses for different clock domains correspond to the order and spacing of the clock pulses of the slow clock signal.

A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

One exemplary embodiment describes an integrated circuit, comprising a multiplicity of scan flip-flops, a multiplicity of ring oscillator circuits, wherein each ring oscillator circuit comprises a chain of logic gates comprising a plurality of logic gates connected in succession, an input multiplexer for the chain, and a feedback line from an output connection of the last logic gate of the chain to a data input connection of the input multiplexer. Each ring oscillator circuit is assigned a scan flip-flop group that contains at least one of the multiplicity of scan flip-flops. The input multiplexer of the ring oscillator circuit is controlled depending on a control bit stored by the at least one scan flip-flop of the scan flip-flop group assigned to the ring oscillator circuit such that the input multiplexer outputs an output bit fed back via the feedback line to the first logic gate of the chain or that the input multiplexer outputs a input bit that is to be processed by the chain to the first logic gate of the chain. The ring oscillator circuits are assigned different scan flip-flop groups.

A semiconductor device of the embodiment includes a plurality of scan chains, a shift clock control circuit, and a shift clock generation circuit. The plurality of scan chains each include a plurality of scan flip-flops. The shift clock control circuit outputs, to each of the plurality of scan chains, a control signal that non-inverts or inverts a scan clock signal. The shift clock generation circuit is provided to each of the plurality of scan flip-flops and generates a non-inverted scan clock signal or an inverted scan clock signal based on the control signal, the non-inverted scan clock signal being obtained by non-inverting the scan clock signal, the inverted scan clock signal being obtained by inverting the scan clock signal.

Described herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using a same scan chain compressor-decompressor circuit may be performed. Also disclosed herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using multiple different scan chain compressor-decompressor circuits may be performed.