A method for testing a chip comprising: receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.

In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.

A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.

A tool for performing a logic built-in self-test of an electronic circuit operating on a clock cycle basis. The tool stores a configurable test signature in a random-access memory together with a pattern counter for a test pattern, wherein a number of the at least one additional signature register corresponds to a number of entries in the random access memory. The tool determines an error based, at least in part, on a compare operation for a given test pattern, wherein the compare operation determines whether the test signature in the first signature register before a capture cycle of a next test pattern differs from the corresponding configurable test signature. The tool stores the error in a corresponding additional signature register.

A method for testing a chip comprising receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.

A method for testing a signal path in a sensor, the signal path including a filter circuit and a comparator circuit, the method including: closing a first signal line that is arranged to bypass a first capacitor in the filter circuit; injecting a test signal into the signal path after the first signal line is closed; and detecting whether a signal that is output by the comparator circuit in response to the test signal satisfies a predetermined condition.

A test circuit for testing an integrated circuit includes a plurality of normal flip flops and a modified flip flop, wherein the integrated circuit includes a black box circuit and a plurality of combinational logic circuits. The normal flip flops each includes a first input pin, a second input pin and a first output pin and is configured to temporarily store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The modified flip flop includes a third input pin, a fourth input pin and a second output pin which are coupled to the black box circuit, the normal flip flops and the combinational logic circuits and is configured to temporarily store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.

A circuit system includes a first circuit, a second circuit, and a comparator. The second circuit and the first circuit have substantially identical structures. In a testing mode, the circuit system controls the first circuit and the second circuit to perform the same testing operation synchronously. During the process of the testing operation, the comparator keeps compares a first intermediate signal internally generated by the first circuit and a second intermediate signal corresponding to the first intermediate signal that is internally generated by the second circuit. When the first intermediate signal is different from the second intermediate signal, the circuit system controls the first circuit and the second circuit to stop the testing operation and controls the first circuit and the second circuit to perform a scan dump operation in order to record signals transmitting by the first circuit and signals transmitting by the second circuit.

Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

A method tests at least three devices, each device including a test chain having a plurality of positions storing test data. The testing includes comparing test data in a last position of the test chain of each of the devices, and shifting test data in the test chains of each of the devices and storing a result of the comparison in a first position of the test chains of each of the devices. The comparing and the shifting and storing are repeated until all the stored test data has been compared. The at least three devices may have a same functionality and a same structure.