System and method for performing scan test on multiple IC devices by site-multiplexing. Multiple test sites of an ATE are coupled to multiple DUTs through a multiplexer. A scan test includes a scan-in/out phase and consecutive launch/capture cycles. Each site performs scan in/out in parallel on the corresponding DUT. In each launch/capture cycle, a respective site drives/captures data from a DUT while the remaining sites are inactive. The multiplexer allows the active site to borrow test channels assigned to other test sites such that all the test data of a DUT can be driven/captured in the launch capture cycle despite the test channel limitation of the active test site. As the tester channels receive interleaved data of the multiple sites, each strobe edge of a receive channel is assigned to a particular test site and used to quickly identify a failure site without post-processing test data.

System and method for performing scan test on multiple IC devices by site-multiplexing. Multiple test sites of an ATE are coupled to multiple DUTs through a multiplexer. A scan test includes a scan-in/out phase and consecutive launch/capture cycles. Each site performs scan in/out in parallel on the corresponding DUT. In each launch/capture cycle, a respective site drives/captures data from a DUT while the remaining sites are inactive. The multiplexer allows the active site to borrow test channels assigned to other test sites such that all the test data of a DUT can be driven/captured in the launch capture cycle despite the test channel limitation of the active test site. As the tester channels receive interleaved data of the multiple sites, each strobe edge of a receive channel is assigned to a particular test site and used to quickly identify a failure site without post-processing test data.

A data failure detection circuit of embodiments includes a monitor signal generation circuit configured to generate a monitor signal to be used to sense failures of a plurality of test mode signals to be respectively input to a plurality of modules, a cascade connection circuit configured to sense a failure of each of the test mode signals and including a plurality of OR circuits, and a comparison circuit configured to compare an output signal from the cascade connection circuit with the monitor signal to determine whether or not a failure exists. In the cascade connection circuit, a plurality of OR circuits are connected in cascade, and the monitor signal is input to one of the OR circuits in a first stage.

Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a complete test setthat is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.

A test apparatus for generating reference scan chain test data comprises a test pattern generator and an output data modifier. The test pattern generator modifies a scan chain test input bit sequence by replacing a predefined number of start bits of the scan chain test input bit sequence by a predefined start bit sequence. Further, the test pattern generator provides the modified scan chain test input bit sequence to a device under test. The output data modifier modifies a scan chain test output bit sequence received from the device under test and caused by the modified scan chain test input bit sequence. The scan chain test output bit sequence is modified by replacing a predefined number of end bits of the scan chain test output bit sequence by a predefined end bit sequence to obtain the reference scan chain test data.

A method for tracking and managing activities of testbench components in a test environment during a simulation is disclosed. In some embodiments, the method includes receiving a first Activity Tracking Unit (ATU) message from an ATU pre-installed within each of a plurality of testbench components. The method further includes registering each of the plurality of testbench components in response to receiving the first ATU message from the corresponding ATU. The method further includes selecting one or more configuration settings corresponding to the ATU of each of the plurality of testbench components based on one or more user requirements. The method further includes receiving at least one second ATU message from the corresponding ATU based on the one or more configuration settings, at an end of the simulation. The method further includes utilizing the at least one second ATU message to drive one or more outcomes corresponding to the simulation.

A digital circuit includes a scan chain which loads data into and unloads data from the digital circuit. Checking circuitry is coupled to the scan chain and generates a first digital signature based on data indicative of a pre-testing status of the digital circuit as the data is unloaded from the digital circuit via the scan chain. When testing is completed, the data is restored to the digital circuit via the scan chain. The checking circuitry generates a second digital signature as the data is loaded into the digital circuit. The first digital signature is compared to the second digital signature to verify an integrity of the process. A specific data pattern may be loaded into the scan chain as the data is unloaded. An output of the scan chain may be monitored to detect the pattern and an error signal may be generated based on when the pattern is detected.

A circuit debugging method includes: utilizing a debugging circuit to determine an operating status of a specific circuit to generate a result; utilizing a register located in a scan chain path to store the result, wherein the scan chain path is arranged for a scan test; and utilizing an output pad located in the scan chain path to output the result, wherein the result is arranged to be indicative of the operating status of the specific circuit.

A serial interface circuit includes an input/output (I/O) port to receive data and a control circuit configured to load a delay metric for the serial interface circuit, transmit first control information of the delay metric to a monitor circuit to cause the monitor circuit to generate a plurality of delay time measurement values, sort the plurality of delay time measurement values to generate sorted values, generate a look-up table (LUT) by mapping the sorted values to indices and transmit the LUT to the monitor circuit.

A vehicle includes a plurality of electronic control units (ECUs), and determines whether any of the ECUs are read/write protected. The vehicle includes control circuitry that is configured to determine a data protection setting for at least one ECU, generate a diagnostic code indicator based on the data protection setting, and generate a visual indicator based on the diagnostic code indicator.