A processor comprises an exchange, a plurality of columns, and a plurality of exchange scan chains. The exchange comprises a plurality of exchange paths, each comprising a set of exchange path portions, for transmitting data between processing units. Each of the plurality of column comprises processing units, each processing unit connected to output data to a respective exchange path, and column pipe circuitry for providing a controllable path between the exchange and the processing units. The column pipe circuitry comprises a column wrapper chain for preventing a scan test signal from passing between the exchange paths and the processing units. The exchange scan chains enable scan testing of the exchange paths. Each exchange scan chain comprises a plurality of scan chain segments, each scan chain segment comprises an exchange path portion connected to at least one of the processing units of at least one of the columns of the processor.

A combinational circuit block has input pins configured to receive input digital signals and output pins configured to provide output digital signals as a function of the input digital signals received. A test input pin receives a test input signal. A test output pin provides a test output signal as a function of the test input signal received. A set of scan registers are selectively coupled to either the combinational circuit block or to one another so as to form a scan chain of scan registers serially coupled between the test input pin and the test output pin. The scan registers in the set of scan registers are clocked by a clock signal. At least one input register is coupled between the test input pin and a first scan register of the scan chain. The at least one input register is clocked by an inverted replica of the clock signal.

One aspect provides an FPGA chip mounted on a printed circuit board (PCB). The FPGA chip can include a joint test action group (JTAG) interface comprising a number of input/output pins and an enablement pin, and a control logic block coupled to the enablement pin of the JTAG interface. The control logic block can receive a control signal from an off-chip control unit and control a logical value of the enablement pin based on the received control signal, thereby facilitating the off-chip control unit to lock or unlock the JTAG interface. The FPGA chip can further include a detection logic block to detect an unauthorized access to the FPGA chip. An input to the detection logic is coupled to the enablement pin, and a conductive trace coupling the input of the detection logic block and the enablement pin is situated on an inner layer of the PCB.

An Integrated Circuit (IC) includes a storage element and control circuitry. The control circuitry is configured to select, responsively to a scan-enable control, between a functional-data input and a scan-data input to serve as an input to the storage element, to selectively disable toggling of an output of the storage element, responsively to a clock-enable control, by gating a clock signal provided to the storage element, and, while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, to select the input of the storage element to be the scan-data input.

The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.

A system comprises a memory sub-system controller mounted to a printed circuit board (PCB) and an in-circuit test (ICT) device. The memory sub-system controller has test points on the PCB comprising stimulus points and observation points. The ICT device connects to the test points of the controller. The ICT device converts automated test pattern generation (ATPG) input test vectors to test signals. A first set of pin drivers of the ICT device applies the test signals to the stimulus points of the controller and a second set of pin drivers of the ICT device read output signals output at the observation points of the controller. A comparator of the ICT device compares the output signals with output test vectors. The comparator provides test result data comprising a result of the comparison.

A boundary scan test method and a storage medium are disclosed. The method can be capable of testing the connectivity of a pad having a direct connection to user logic. The method is preformed based on a scan test instruction to FPGA. According to the method of the invention, software configuration is performed in FPGA user logic with respect to a PAD to be tested, such that the PAD can be tested according to the configuration without the need to test or pass through PADs that do not need to be tested. The method shortens boundary scan chains, thereby enabling rapid and flexible boundary scan tests and improving test efficiency.

Example embodiments are disclosed of systems and methods for predicting failure probabilities of future product tests of a testing sequence based on outcomes of prior tests. Predictions are made by a machine-learning-based model (MLM) trained with a set of test-result sequence records (TRSRs) including test values and pass/fail indicators (PRIs) of completed tests. Within training epochs over the set, iterations are carried out over each TRSR. Each iteration involves sub-iterations carried out successively over test results of the TRSR. Each sub-iteration involves (i) inputting to the MLM values of a given test and those of tests earlier in the sequence while masking those later in the sequence, (ii) computing probabilities of test failures for the masked tests found later in the sequence than the given test, and (iii) applying the PFIs of test results later in the sequence than the given test as ground-truths to update parameters of the MLM.

An electronic device includes a processing unit with a memory, a JTAG interface with test-data-input and test-mode-select lines coupled to the processing unit, a bridge circuit, and a multiplexer circuit. The bridge circuit includes a serial communication interface receiving a serial data input signal which conveys an input serial data frame. The bridge circuit includes a serial-to-parallel converter circuit block receiving the input serial data frame, processing the input serial data frame to read first and second subsets of input binary values therefrom, and transmitting the first subset via a first output signal and the second subset via a second output signal. The multiplexer circuit selectively propagates a received test-data-input signal or the first output signal to the test data input line, and selectively propagates a test-mode-select signal or the second output signal to the test mode select line of the JTAG interface.

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.