Patent classifications
G01R31/318577
Wafer with dio bidirectional lead, n dies, domains, clock leads
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
TSV TESTING USING TEST CIRCUITS AND GROUNDING MEANS
This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.
Method and system for monitoring quality and controlling an alternating current power supply provided to an ultrasound system from a power outlet
A system and method for monitoring quality and controlling an AC power supply provided to medical equipment from a power outlet is provided. The method includes analyzing a digital signal to determine AC power supply quality characteristics of a corresponding AC power input received and converted to the digital signal at an AC power supply quality monitoring system. The method includes presenting the AC power supply quality characteristics at a display of the AC power supply quality monitoring system. The method includes determining whether the AC power supply quality characteristics are within a threshold quality range. The method includes activating a block at a protection circuit of the AC power supply quality monitoring system if the AC power supply quality characteristics are outside of the threshold quality range. The block at the protection circuit prevents the AC power input from being output from the AC power supply quality monitoring system.
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
TSV first ends connected to test stimulus and response signals
This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.
METHOD AND SYSTEM FOR MONITORING QUALITY AND CONTROLLING AN ALTERNATING CURRENT POWER SUPPLY PROVIDED TO AN ULTRASOUND SYSTEM FROM A POWER OUTLET
A system and method for monitoring quality and controlling an AC power supply provided to medical equipment from a power outlet is provided. The method includes analyzing a digital signal to determine AC power supply quality characteristics of a corresponding AC power input received and converted to the digital signal at an AC power supply quality monitoring system. The method includes presenting the AC power supply quality characteristics at a display of the AC power supply quality monitoring system. The method includes determining whether the AC power supply quality characteristics are within a threshold quality range. The method includes activating a block at a protection circuit of the AC power supply quality monitoring system if the AC power supply quality characteristics are outside of the threshold quality range. The block at the protection circuit prevents the AC power input from being output from the AC power supply quality monitoring system.
Wafer tap domain die channel circuitry with separate die clocks
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
Boundary scan testing a storage device via system management bus interface
A system and method are provided for boundary scan testing one or more digital data storage drives. In particular, a drive tester system connects to the one or more digital data storage drives via a standard two-wire interface, such as a system management bus (SMBus) interface. The drive tester system performs a boundary scan test on the on more digital data storage drives via the standard two-wire interface. The boundary scan test may include a vector test.
SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS
Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.
Scan circuitry with IDDQ verification
An integrated circuitry includes a first logic block coupled between a first power supply terminal and a second power supply terminal. The first logic block includes a first scan chain and a configurable defect coupled to a scan output node of the first scan chain. The configurable defect has a logic node and a conductive element coupled between the logic node and the first or the second power supply terminal. The configurable defect is configured to, during a quiescent current testing mode, place a predetermined logic state on the logic node such that a current flows through the conductive element. The current can be detected by external equipment.