Stacked circuits are configured to facilitate post-stacking testing. According to one example, a stacked circuit may include a first die electrically coupled to a second die through a plurality of interconnects. The first die may include a test input interface configured to receive test data signals and a source test clock signal, a test output interface configured to convey test responses, a first test signal path, at least one first die-to-die output interface configured to convey to the second die the test data signals and a low-latency clock signal received from a low-latency clock path between the test input interface and the at least one first die-to-die output interface, and at least one first die-to-die input interface configured to receive test responses and the clock signal from the second die. Other aspects, embodiments, and features are also included.

This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

A circuit comprises a plurality of clock control devices. Each of the clock control devices is configured to generate a scan test clock signal for a particular clock domain in the circuit and comprises circuitry configured to select clock pulses of a fast clock signal as scan capture clock pulses for the particular clock domain based on a particular clock pulse of a slow clock signal and a scan enable signal. The order and spacing between the groups of the scan capture clock pulses for different clock domains correspond to the order and spacing of the clock pulses of the slow clock signal.

A scan test device includes a scan flip flop circuit and a clock gating circuit. The scan flip flop circuit is configured to receive a scan input signal according to a scan clock signal, and to output the received scan input signal to be a test signal. The clock gating circuit is configured to selectively mask the scan clock signal according to a predetermined bit of the test signal and a scan enable signal, in order to generate a test clock signal for testing at least one core circuit.

Disclosed herein is a pseudo-random binary sequence (PRBS) generator (200) for performing on-chip testing. It comprises of a plurality of lanes (L1-L4), wherein each lane comprises a latch group (Lg1-Lg4) capable of receiving clock signals, wherein a number of latches in each latch group is based on an output sequence to be generated for performing the on-chip testing. Each latch group is having at least one of a flip-flop and a latch is further connected with a plurality of logic gates in such a manner that an output, generated by the at least one of the flip-flop and the latch of each latch group, is provided as an input to the plurality of logic gates.

The disclosure relates to a scan chain circuit comprising cascaded flip-flops having a functional input node and a test input node configured to be selectively coupled to logic circuitry at a clock edge time. A clock line is provided configured to distribute one or more clock signals to the flip-flops in the chain, wherein the flip-flops in the chain have active clock edges applied thereto at respective clock edge times. The chain of flip-flops comprise a set of flip-flops configured to receive an edge inversion signal and to selectively invert their active clock edges in response to the edge inversion signal being asserted.

An integrated circuit includes a ring oscillator circuit and a plurality of logic paths. Each logic path comprises a path input connection, a path output connection and an input multiplexer, which has an output connection that is connected to the path input connection of the logic path. Each logic path, beginning with a first logic path, is assigned a respective subsequent logic path by virtue of the path output connection of the logic path being connected to a data input connection of the input multiplexer of the subsequent logic path. A last logic path of the logic paths is assigned the first logic path as subsequent logic path. For each logic path, the multiplexer is configured such that, when a control signal that indicates a test mode is fed thereto, it connects the data input connection of the input multiplexer to the path input connection of the logic path.

This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.