Embodiments of the present invention provide an automated test equipment (a “tester”) for testing a device under test, including a bidirectional dedicated real-time handler interface. Some embodiments include an interface having a trigger function, a fixed endpoint interface, an interface arranged on a test head, and/or a number of lines/communication channels adapted to a specific communication task, without separate signal lines, for example. The bidirectional dedicated real-time handler interface can be used to transmit a synchronization signal or other information to the handler in real-time, and the transmitted signal can be test site specific. The real-time signaling advantageously improves testing accuracy and efficiency.

Embodiments of the invention include a method of preparing an integrated circuit (IC) chip to participate in test operations. The method includes accessing a back surface of the IC chip and adding a back-surface topography to the back surface. A surface area of the back-surface topography is greater than a surface area of the back surface.

The present disclosure provides an electronic tester comprising at least one test fixture that couples to a device under test, at least one test instrument coupled to at least one of the test fixtures that measures signals in the device under test, a test controller that controls the device under test while the test is performed, and an adapter module comprising a general control interface that is coupled to the test controller, and a DUT-specific communication interface that couples to the device under test to communicate with the device under test, wherein the test controller controls the device under test with generic control signals sent to the general control interface, and wherein the adapter module translates the general control signals into DUT-specific control signals and transmit the DUT-specific control signals to the device under test. Further, the present disclosure provides a respective method.

A system for programming integrated circuit (IC) dies formed on a wafer includes a magnetic field transmitter that outputs a digital test program as a magnetic signal. At least one digital magnetic sensor (e.g., Hall effect sensor) is formed with the IC dies on the wafer. The digital magnetic sensor detects and receives the magnetic signal. A processor formed on the wafer converts the magnetic signal to the digital test program and the digital test program is stored in memory on the wafer in association with one of the IC dies. The magnetic field transmitter does not physically contact the dies, but can flood an entire surface of the wafer with the magnetic signal so that all of the IC dies are concurrently programmed with the digital test program.

A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

A system includes probe pins each including a probe tip and a plurality of thermocouples arranged such that at least one thermocouple is positioned between a pair of the probe pins. The plurality of thermocouples can be placed adjacent or above a device under test (DUT). The probe tips of the probe pins are placed over a plurality of pads. The plurality of thermocouples are placed adjacent or between the plurality of pads. The at least one thermocouple positioned between the pair of the probe pins can be either a single thermocouple or a thermocouple array.

A testing apparatus comprises a test interface board comprising a plurality of socket interface boards, wherein each socket interface board comprises: a) an open socket to hold a DUT; b) a discrete active thermal interposer comprising thermal properties and operable to make thermal contact with the DUT; c) a superstructure operable to contain the discrete active thermal interposer; and d) an actuation mechanism operable to provide a contact force to bring the discrete active thermal interposer in contact with the DUT.

The invention relates to a test block intended to be implanted in the circuit connecting an apparatus to be tested such as an electricity meter or a protective relay and a power source supplying the apparatus to be tested such as an intensity sensor and/or a voltage sensor. The test block comprises a base including a plurality of inner electric circuits capable of allowing the transmission of information from the power source to the apparatus to be tested and a protective cover intended to be assembled in a dismountable manner with the base in order to form a closed enclosure in which the inner electric circuits are housed. The base and the protective cover are configured such that the removal of the protective cover gives access to a receiving site delimited by the base and capable of receiving by plugging a test plug independent of the test block and electrically linked to a test equipment, in particular a voltmeter and/or an ammeter and/or a dummy current source. A test appliance is also described.

There is described a test block intended to be implanted in the circuit connecting an apparatus to be tested such as an electricity meter or a protective relay and a power source supplying the apparatus to be tested such as an intensity sensor and/or a voltage sensor, the test block comprising a base including a plurality of inner electric circuits capable of allowing the transmission of information from the power source to the apparatus to be tested and a protective cover intended to be removably assembled with the base in order to form a closed enclosure in which the inner electric circuits are housed. The base and the protective cover are configured such that the removal of the protective cover gives access to a receiving site delimited by the base and capable of receiving, by plugging, a test plug independent of the test block and electrically linked to a test equipment, in particular a voltmeter and/or an ammeter and/or a dummy current source. The base and the protective cover comprise electrically conductive elements linked to each other and configured so as to ensure a continuity and magnetic shielding closure such that the enclosure delimited by the base and the protective cover is a Faraday cage protecting the inner electric circuits relative to the magnetic fields external to the enclosure delimited by the base and the protective cover.

A method for testing a device under test at a specific channel condition is provided. The method comprises the steps of initiating a communication with the device under test and receiving a transmission frame from the device under test with a header portion comprising a specific transmission rate information. It also comprises analyzing the header portion of the transmission frame in order to determine whether the device under test is transmitting with the specific transmission rate information.