This application is related to a measuring system and method for performing various measurement tasks. The measuring system comprises a test-setup configured to measure the characteristics of a device-under-test and an input-device of the test-setup configured to receive a test-case. The measuring system further comprises several measurement-hardware devices configured to perform the measurements according to the test-case. A computer unit of the measuring system is configured to determine at least one required hardware device on the basis of the test-case and to select the additional measurement-hardware devices. The computer unit is further configured to identify an adding of the selected additional measurement-hardware.

An error rate measuring apparatus includes a data transmission unit that transmits a test signal of a known pattern and a parameter value defined by a communication standard to a device under test, and a bit error measurement unit that measures a bit error of a signal transmitted from the device under test. The data transmission unit sequentially changes the parameter value and transmits the parameter value to the device under test. The bit error measurement unit measures a bit error of a signal transmitted from the device under test corresponding to the parameter value. The error rate measuring apparatus further includes a discrimination unit that discriminates a parameter value at which the number of bit errors is the least in a measurement result of the bit error measurement unit, as an optimum value of emphasis of an output waveform of the device under test.

Non-standard sector size system support for SSD testing. An automated test equipment for simultaneous testing of multiple solid state drives (SSDs), wherein the SSD has a sector size that is not an integral power of two, includes a tester block configured to receive a command to read and verify an amount of data from the SSD starting at a starting address. The starting address is not constrained to correspond to a sector boundary and the amount of data is not constrained to be an integral multiple of the SSD data sector size. The test equipment also includes logic within said tester block configured to determine a starting sector of the SSD that the starting address points to, and logic within said tester block configured to determine a number of sectors required for the amount of data to be read. The tester block is configured to read a sector from the SSD. The test equipment further includes a pattern generator configured to generate a pseudo-random sequence of data based on a sector number of the SSD, and logic configured to compare the data read from the SSD to the pseudo-random sequence of data.

Systems and methods are disclosed for testing a device under test (DUT) by receiving a test pattern for a functional test, wherein the test pattern includes a test vector, an expected test result, and an expected power consumption; instructing the test system to run a repetitive loop using a selected functional test as the stimulus; at selected steps in the functional test, measuring power consumption of the DUT; and validating the DUT based on validating the test vector and the power consumption with one or more expected test result patterns and expected power consumption patterns.

The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes: a controller processor, a plurality of programmable accelerator circuits, and a plurality of load boards respectively. The plurality of programmable accelerator circuits providing input test signals and capture output test signals. The plurality of load boards apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. In one exemplary implementation, each of the plurality of load boards includes a first set of connections that transmit input test signals to a respective DUT, a second set of connections that receive output test signals from the respective DUT, and sideband connectors. The sideband connectors receive test related information from the DUT.

An automated test equipment (ATE) apparatus comprising a tester processor operable to generate commands and data for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises an FPGA communicatively coupled to the tester processor, wherein the FPGA comprises routing logic operable to route signals associated with the commands and data in the FPGA based on a type of the DUT. Further, the ATE comprises a connector module communicatively coupled to the FPGA comprising a socket to which the DUT connects and further comprising circuitry for routing the signals to a set of pins on the DUT, wherein the set of pins are associated with a first type of DUT. The circuitry can support multiple different DUT types having a common form factor but different pinout assignments.

A method for testing DUT comprises receiving instructions from a system controller at a tester board, wherein the tester board comprises an FPGA and the tester processor are coupled to the system controller, and wherein the tester processor is operable to coordinate testing of a device under test (DUT). The method further comprises generating commands and data for testing the DUT and routing signals associated with the commands and the data in the FPGA based on a type of the DUT. Also, the method comprises transmitting the signals over lanes corresponding to a particular set of pins on the DUT, wherein the particular set of pins depend on the type of the DUT.

A virtualizable automated test equipment architecture includes a circuit assembly. The circuit assembly includes a number of signal paths that extend between a front plane and a backplane. The signal paths can be continuous and isolated from other signal paths of the plurality of signal paths. The circuit assembly also includes an impedance disposed along a signal path of the plurality of signal paths. A plurality of software-configurable physical disconnects may be arranged within the circuit assembly to form a switching matrix. The plurality of signal paths can be associated with a plurality of software-configurable physical disconnects, which can be configured to open and close signal paths of the plurality of signal paths based on the predetermined test requirements. The circuit assembly also includes a plurality of external device connections, at least one of which may be configured to interface with a unit under test (UUT). The software configurable physical disconnects may be configurable at runtime. Because the system if virtualizable, multiplied UUTs may be tested simultaneously according to different requirements, and the testing may be executed on shared hardware in a manner transparent to the UUTs.

A test board includes a first board and a second board. The first board includes a socket on which a device under test (DUT) is mounted, and a first functional circuit. The first functional circuit exchanges signals and data with the DUT in an actual operating environment of the DUT, and performs a first test on the DUT using a first test signal. The first test signal is identical to a signal to be transmitted in the actual operating environment. The second board includes a processor and a multiplexer. The processor performs a second test different from the first test on the DUT using a second test signal. The second test signal is different from the first test signal and checks an electrical characteristic of the DUT itself. The multiplexer selects one of the first test signal and the second test signal to transmit to the DUT.

The invention concerns a test program executor for an Automated Test Equipment, wherein the test program executor is configured to execute a test flow having a plurality of test suites, wherein the test program executor is configured to asynchronously execute the plurality of test suites, wherein a test suite contains a call of a function of a subsystem, wherein the function of the subsystem is related with a subsystem operation that is to be executed by the subsystem, and to signal a call of a function of a subsystem by transmitting an asynchronous request to the subsystem, the asynchronous request having a call-specific call tree hierarchy address and the call-specific operation to be executed by the subsystem, and wherein the test program executor is further configured to determine an execution order of the subsystem operations, such that the execution order of the subsystem operations depends on their call-specific call tree hierarchy addresses.