A digital circuit robustness verification method is provided that includes the following steps. An internal storage circuit and an external storage circuit corresponding to a circuit under test are set to store a plurality of random values and a configuration of the circuit under test for performing a predetermined function is set by a processing circuit. A driving signal corresponding to the predetermined function is transmitted to the circuit under test by a previous stage circuit, such that the circuit under test executes the predetermined function to further generate an output signal. The determination as to whether the output signal is correct or not is made by a next stage circuit, and the circuit under test is determined to pass a robustness verification when the output signal is correct.

The automated test equipment is configured to establish communication, e.g. by uploading a program to the DUT using a first interface, such as a debug interface or a generic interface having access to the processing unit for external control. A typical use case of the first interface is debug access to the DUT, which typically requires limited data rates. In the case of the invention the first interface is an ATE access for test execution. The first interface configures the DUT to open a second interface running at much higher data rate, which is higher than the first interface, for additional communication. Additionally, the second interface may have extended capabilities compared to the first interface, such as presenting its own memory to the processing unit of the DUT as a normal system memory.

Systems, integrated circuits and methods for synchronizing testing a Device under test (DUT) with an automated test equipment (ATE) is provided. In one example, a method includes transmitting a test packet from an ATE to a first Device Under Test DUT; receiving, at the ATE from the DUT, a result packet; and in response to receiving a Start of Packet (SOP) indicator from the DUT at the ATE, evaluating the first DUT by comparing the result packet to an expected packet associated with the test packet.

The invention relates to a universal semiconductor automatic high-speed serial signal testing method, comprising: a chip to be tested sending, to an impedance matching unit, a high-speed serial signal; then by means of a phase shift unit, sequentially transforming, according to a set fixed resolution, the phase of the high-speed serial signal, the magnitude of each offset phase being determined by a phase shift control signal outputted by a control unit and the resolution of the phase shift unit; after passing through the phase shift unit, the high-speed serial signal keeps channel impedance matching by means of the impedance matching unit; the signal entering an acquisition unit, and being acquired under the action of an acquisition control signal sent by the control unit; the control unit performing signal exchange with semiconductor automatic testing equipment (ATE); and the acquisition unit transmitting the acquired signal back to the universal semiconductor ATE for algorithm operation, and then the actual high-speed serial data stream is obtained. The present invention enables direct testing of high-speed serial interface signals by means of the universal ATE during mass production, greatly improving testing convenience and efficiency.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a test system comprises pre-qualifying test components, functional test components, a controller, a transceiver, and a switch. The pre-qualifying test components are configured to perform pre-qualifying testing on a device under test. The functional test components are configured to perform functional testing on the device under test. The controller is configured to direct selection between the pre-qualifying testing and functional testing. The transceiver is configured to transmit and receive signals to/from the device under test. The switch is configured to selectively couple the transceiver to the pre-qualifying test components and functional test components.

A method includes identifying state holding pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design, splitting each pattern of a plurality of patterns into a first part and a second part, reformatting the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns. The length of the first part is a function of a number of the identified pipeline stages.

A system for over-the-air testing of a device under test includes a measurement antenna, a reference antenna, a device under test capable of wirelessly transmitting and/or receiving complex radio frequency signals, and an analyzer. The analyzer has at least two ports, wherein the reference antenna is connected with a first port of the analyzer. The measurement antenna is connected with a second port of the analyzer. The analyzer is capable of determining a phase difference and a power ratio of radio frequency signals received via the measurement antenna and the reference antenna. The analyzer is capable of performing an IQ analysis on complex radio frequency signals. Further, a method of over-the-air testing of a device under test is disclosed.

A test equipment is provided for over the air tests on a device under test, in particular a user equipment, having a shielded space, at least one signal antenna for transmitting and receiving cellular signals arranged in the shielded space, and a plurality of noise antennas arranged in the shielded space linked in an array configured to create Additive White Gaussian Noise. The noise antennas are equally distributed in three dimensions within the shielded space. Further, a method for testing a device under test is shown.

A test apparatus for performing a test on a device under test includes a data storage unit being configured to store sets of input data applied to the device under test during the test and to store the respective output data of the device under test, the output data being obtained from the device under test as a response to the input data including values of setting variables related to settings of the device under test and values of input variables including further information, each set of input data representing one test case; and a data processor configured to process the data stored in the data storage unit such that a best combination of setting variables of the device under test is determined for one or more combinations of the input variables to obtain an optimized setting of the device under test for the one or more combinations of the input variables.

A testing probe system includes probes configured to contact shared probe pads of multi-channel die of a wafer; and a controller configured to generate testing patterns and receive signals from the multi-channel die of the wafer. The controller is configured to contact a probe of the probes with a shared probe pad of the multi-channel die, select a first channel of the multi-channel die to test, select at least one test mode for testing the first channel, stimulate at least the first channel during a single contact period, acquiring a first output of the first channel during the single contact period, select a second channel of the multi-channel die to test, select at least one test mode for testing the second channel, stimulate at least the second channel during the single contact period, and acquire a second output of the first channel during the single contact period.