The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes: a controller processor, a plurality of programmable accelerator circuits, and a plurality of load boards respectively. The plurality of programmable accelerator circuits providing input test signals and capture output test signals. The plurality of load boards apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. In one exemplary implementation, each of the plurality of load boards includes a first set of connections that transmit input test signals to a respective DUT, a second set of connections that receive output test signals from the respective DUT, and sideband connectors. The sideband connectors receive test related information from the DUT.

A test device includes a test mounting circuit having a plurality of semiconductor devices mounted thereon as respective devices-under-test. Each device-under-test includes a corresponding delay control circuit and a target circuit therein. Test logic is provided, which is electrically coupled to the test mounting circuit. The test logic is configured to generate a test input(s), which is provided in parallel to the delay control circuits within the plurality of devices-under-test. The delay control circuits include at least first and second delay control circuits, which are configured to pass the test input(s) to corresponding first and second target circuits during respective first and second test time intervals that are out-of-phase relative to each other in order to achieve more uniform power consumption requirements of the test mounting circuit during testing.

Apparatus for testing an integrated circuit is described, including a set of signal conductors for communicating signals to respective external conductors of the integrated circuit. The apparatus also includes a tester comprising circuitry for outputting a signal. An interposer is electrically coupled between the set of signal conductors and the tester. The interposer comprises circuitry for selecting a set of signals between the set of signal conductors and the tester and outputting the set of signals. A signal processing apparatus is coupled to receive the set of signals, and the signal processing apparatus is operable to evaluate a parameter associated with each signal in the set of signals.

The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYs (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC) production cycles.

A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.

A system and method are provided for testing features of an embedded system. The system includes a low-powered computing device communicatively coupled to a control application interface, a sensor interface, and a robotic interface. The low-powered computing device may receive sensor signals generated during a test, provide sensor data corresponding to the sensor signals, receive commands for the test, and provide instructions for movement of a robotic handler corresponding to at least one of the commands for the test. The system also includes a computing device communicatively coupled to the control application interface, an image processing interface, and a database interface. The computing device may receive sensor data, receive image data corresponding to images of the embedded system captured during the test, receive tests capable of being performed, and provide commands for the test.

An automated test equipment (ATE) system capable of performing a test of semiconductor devices is presented. The system comprises a first test board including a first FPGA communicatively coupled to a controller via an interface board, wherein the first FPGA comprises a first core programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a DUT. The system also includes a second test board comprising a second FPGA communicatively coupled to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for a device under test, wherein the second FPGA is further programmed to simulate a DUT, and wherein the first FPGA is operable to communicate with the second FPGA in order to test a communication link between the first test board and the second test board.

A measurement system of a device under test (DUT) includes a reference clock synthesizer configured to generate a master reference clock signal, a transmitter unit connected to the reference clock synthesizer and configured to connect to the DUT, and a measurement control system connected to the transmitter unit and configured to control the transmitter unit to generate a test signal pattern based on a first reference clock signal derived from the master reference clock signal, and generate a signal for passing through the DUT based on the test signal pattern. A receiver unit connected to the reference clock synthesizer is configured to connect to the DUT and to detect the signal and generate a digital signal based on the signal and a second reference clock signal derived from the master reference clock signal. The measurement control system is configured to provide an output signal based on the digital signal.

A test system for testing a device under test that includes several communication lanes is described. The test system is a communication lane test system that includes a measurement instrument and a connecting interface for connecting the device under test, wherein the connecting interface is configured to connect at least two of the several communication lanes with the measurement instrument. The measurement instrument includes s a processor being configured to conduct an automatic conformance test on the at least two communication lanes concurrently. Moreover, a method for testing a device under test that includes s several communication lanes is described.

An automated test equipment (ATE) apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a tester processor and an FPGA. The tester processor is operable to generate commands and data from instructions received from the system controller for coordinating testing of a device under test (DUT), wherein the DUT supports a plurality of non-standard sector sizes and a plurality of protection modes. The FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT, and wherein the at least one hardware accelerator circuit is able to perform computations to calculate protection information associated with the plurality of protection modes and to generate repeatable test patterns sized to fit each of the plurality of non-standard sector sizes.