Embodiments are directed to a semiconductor wafer having on-wafer circuitry. The on-wafer circuitry includes functional circuitry and first drive circuitry communicatively coupled to the functional circuitry. The on-wafer circuitry further includes test-only circuitry communicatively coupled to the functional circuitry, along with second drive circuitry communicatively coupled to the test-only circuitry. The control circuitry is communicatively coupled to the second drive circuitry and the test-only circuitry, wherein the first drive circuitry is configured to drive the functional circuitry in a first manner, and wherein the control circuitry is configured to control the second drive circuitry to drive the test-only circuitry in a second manner that is independent of the first manner.

A ring oscillator (RO) circuit for capturing one or more characteristics relating to aging of CMOS circuitry in a CMOS device has been described. The RO circuit includes a plurality of stages coupled via an RO feedback signal line and forming an inverter chain. The plurality of stages include, for each stage, a respective CMOS inverter comprising a pair of pMOS and nMOS transistors followed by a pass gate, wherein an output of a pass gate for a stage is coupled to an input for the respective CMOS inverter of a next stage. The plurality of stages include an enable stage to enable the inverter chain to be put into a free oscillating mode or another mode in which the RO circuit does not freely oscillate. The plurality of stages include a Device Under Test (DUT) stage preceded by a pre-stage where respective supply rails of the DUT stage and pre-stage are isolated from one another.

Embodiments relate to systems and methods for defect detection and localization in semiconductor chips. In an embodiment, a plurality of registers is arranged in a semiconductor chip. The particular number of registers can vary according to a desired level of localization, and the plurality of registers are geometrically distributed such that defect detection and localization over the entire chip area or a desired chip area, such as a central active region, is achieved in embodiments. In operation, a defect detection and localization routine can be run in parallel with other normal chip functions during a power-up or other phase. In embodiments, the registers can be multi-functional in that they can be used for other operational functions of the chip when not used for defect detection and localization, and vice-versa. Embodiments thereby provide fast, localized defect detection.

An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.

An integrated circuit comprising: a plurality of on-chip-instrument-modules; a test-controller-module configured to communicate data with the plurality of on-chip-instrument-modules; a functional-module configured to communicate data with the plurality of on-chip-instrument-modules; and an on-chip-instrument-controller. The on-chip-instrument controller is configured to: for each of the plurality of on-chip-instrument-modules, store an access-indicator; and based on a value of the access-indicator for each on-chip-instrument-module, enable the on-chip-instrument-module to communicate with either: the test-controller-module; or the functional-module.

Embodiments are directed to a semiconductor wafer having on-wafer circuitry. The on-wafer circuitry includes functional circuitry and first drive circuitry communicatively coupled to the functional circuitry. The on-wafer circuitry further includes test-only circuitry communicatively coupled to the functional circuitry, along with second drive circuitry communicatively coupled to the test-only circuitry. The control circuitry is communicatively coupled to the second drive circuitry and the test-only circuitry, wherein the first drive circuitry is configured to drive the functional circuitry in a first manner, and wherein the control circuitry is configured to control the second drive circuitry to drive the test-only circuitry in a second manner that is independent of the first manner.

Systems and methods for forced early failure of cells within a memory device are disclosed. A memory device such as a dynamic random-access memory (DRAM) chip is subjected to an elevated temperature and an electric field to cause unwanted particles within the chip to migrate rapidly into the circuit elements of a memory cell, thereby causing the memory cell to fail. Subsequent testing may identify this failed cell and verify that the remaining cells within the memory device are operational. By forcing the cell to fail prior to certification testing, the end user may be reasonably confident that the certification provided for the device will remain accurate for the lifetime of the device. In contrast, without this forced early failure, such unwanted particles may migrate after deployment and may cause cell failure while deployed resulting in a botched operation.

A test circuit includes a first input multiplexer configured to receive a first input data signal and a second input data signal, a second input multiplexer configured to receive a first output signal and a third input data signal of the first input multiplexer, a third input multiplexer configured to receive a second output signal and a fourth input data signal of the second input multiplexer, a test block configured to generate an output data signal by performing a test operation based on an output of the third input multiplexer, and a gating circuit configured to receive the output data signal and output the received output data signal to at least one channel.

Methods and apparatus for a diagnostic in situ ring oscillator (RO) circuit for DC and transient characterization. The RO circuit includes a plurality of symmetrical stages coupled via an RO feedback signal line and forming an inverter chain, where each stage includes a CMOS inverter comprising a pair of pMOS and nMOS transistors coupled between power-gating transistors respectively coupled to a positive voltage source and ground, wherein an output of a CMOS inverter for the stage is coupled to an input for the CMOS inverter of a next stage. The first stage is a configurable enable stage to enable the inverter chain to be set into a defined logic state, followed by multiple pre-stage-DUT stages. The output of the last stage is feed back to the input of the enable stage to form an RO feedback signal. The RO circuit can operate in multiple modes including an AC mode, a DC mode, and a hybrid mode.

The present specification discloses a test device, a test system, a test method, and a test apparatus. The test device provided in the present specification includes an FPGA chip capable of controlling a target power supply that supplies power to an MCU under test. In practice, different test logic programs can be configured in the FPGA chip based on actual needs, to satisfy a need of flexibly testing different types of MCUs under test. In addition, the FPGA chip in the test device can be used to generate a high-frequency clock signal, to ensure time accuracy when voltage glitch faults are injected into the MCU under test, so as to further ensure a test effect for the MCU under test.