A method and an apparatus for testing a chip, as well as a storage medium, and a chip thereof are provided. The chip includes an operation module. The method includes receiving, via a first pin of the chip, a test control signal indicating a test type of the operation module; performing a first test for the operation module using a first test vector based on the test type; or performing a second test for the operation module using a second test vector, where the first test is a test for the memory included in the operation module and the second test is a test for the functional logic in included in the operation module.

Some embodiments are directed to a test apparatus for testing a device. The apparatus includes a test device having a memory for storing data processing instructions and processors configured, when the data processing instructions are executed, to execute test code in order to implement a test operation on the device being tested. The test code defines test patterns and test algorithms to be applied to instruments for testing the device being tested, and is in a first format that is independent of the test interface between the test device and the device being tested. The apparatus also includes an interface controller coupled to the device being tested and configured to convert communications generated by the test device during the execution of the test code into a second format suitable for the test interface, and to convert communications from the device being tested into the first format.

An automated test equipment for testing a device under test comprises an on-chip-system-test controller. The on-chip system test controller comprises at least one debug interface or control interface configured to communicate with the device under test. The on-chip-system-test controller optionally comprises at least one high bandwidth interface configured to communicate with the device under test. The on-chip-system-test controller is configured to control a test of a device-under-test which is a system-on-a chip.

An apparatus is provided that includes a control unit and a memory including computer program code. The apparatus is capable of applying a first signal having a first value and a second signal having a second value to an electronic component and receiving a first feedback signal. The apparatus is capable of determining a first parameter associated with the first feedback signal. The apparatus is capable of applying a third signal having a third value and the second signal to the electronic component and receiving a second feedback signal. The apparatus is capable of determining a second parameter associated with the second feedback signal. The apparatus is capable of applying a fourth signal having a fourth value and the second signal to the electronic component if the first parameter is different from the second parameter.

The present disclosure provides a memory device test method, apparatus, and system, a medium, and an electronic device. The memory device test method includes: determining an operation path according to position coordinates of a target test platform and current position coordinates of a memory device; setting a movable apparatus according to the operation path, such that the movable apparatus moves the memory device into the target test platform according to the operation path; controlling the target test platform to test the memory device according to a target test program; and monitoring a test result of the memory device in real time, and storing the test result of the memory device into a database.

In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.

An oscilloscope comprises a number of analog signal inputs for receiving respective analog input signals, an analog-to-digital converter, ADC, for every analog signal input, each ADC comprising an analog input and a digital output, the analog inputs being coupled to the respective one of the analog signal inputs for receiving the respective analog input signal, and the digital outputs outputting respective digital signals, and a signal processor coupled to the digital outputs of the ADCs that performs predetermined signal processing functions based on at least one of the digital signals and outputs a number of respective digital output signals.

In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.

A method, computer program product and/or system is disclosed. According to an aspect of this invention, a device under test (DUT) is switched to a functional test mode. In some embodiments of the present invention, the DUT receives a general scan design (GSD) pattern while in the functional test mode. In some embodiments, the DUT executes a first functional test corresponding to the GSD pattern. In yet other embodiments, the DUT further comprises a state machine that controls the execution of the first functional test. The DUT may further store the output address, the output data, and the status to an address register, a data register, and a status register, respectively and/or send the output address, the output data, and the status to an address register to an automatic testing equipment (ATE).

The present invention has a first step for inputting an inspection signal having a predetermined pattern simultaneously to a plurality of devices connected in parallel to a tester and starting inspection having a predetermined pattern, a second step for determining whether a non-passing device is included in the predetermined pattern, a third step for sequentially executing a predetermined pattern and determining passing/non-passing (PASS/FAIL) status for each of the plurality of devices when it is determined in the second step that a non-passing device is included, and a fourth step for excluding a device determined as non-passing in the third step, subsequent inspection being performed for the devices other than the excluded device.