A solid state switch power emulator circuit, the circuit including a high voltage section including a high voltage power supply (HVPS); a high voltage capacitor (HVC) electronically connected to the HVPS in parallel; a high voltage switch (HVS) electronically connected to the HVC and the HVPS in series; and a high voltage load (HVL) electronically connected to the HVS in series; a low voltage section including a low voltage power supply (LVPS); a low voltage capacitor (LVC) electronically connected to the LVPS in parallel; a low voltage switch (LVS) electronically connected to the LVPS and the LVC in series; a low voltage load (LVL) electronically connected to the LVS in series; and a high voltage diode (HVD) electronically connected to the LVL in series, wherein voltage levels associated with the low voltage section are less than voltage levels associated with the high voltage section.

A pin driver control system for enhancing pulse fidelity can include a first current switch circuit with a current input node and a voltage input node, wherein the first current switch circuit provides a switched output current signal in response to a voltage control signal at the voltage input node. The system can further include a first current source configured to receive a bias control signal and, in response, provide a drive current signal to the current input node of the first current switch. The drive current signal can have a magnitude that exceeds a magnitude of the switched output current signal. The system can further include a bias control circuit configured to receive information about a desired bias current magnitude for use by the first current switch circuit and, in response, provide the bias control signal to the first current source.

A status of one or more components of a battery monitor circuit can be evaluated, such as to validate operation of the monitor circuit. In an example, a battery monitor circuit can be evaluated by providing a first test signal to a battery voltage measurement circuit that is coupled to a battery. A first analog-to-digital converter (ADC) circuit can be configured to receive a first voltage signal from the battery voltage measurement circuit in response to the first test signal. A processor circuit can be configured to validate the first ADC circuit by evaluating a correspondence between the first test signal and the received first voltage signal. One or more other ADC circuits in the battery monitor circuit can be validated by cross-checking measurement results with information from the first ADC circuit.

A system and methods for adaptive bi-direction audio wiring, in which a circuit may be attached via a headset port using RJ9 pin configurations in a phone handset, and dynamically test many different phone handset configurations for optimal audio pathing and processing for speaker and microphone audio generation with minimal noise, static, or power fluctuation.

A method for testing a device under test at a specific channel condition is provided. The method comprises the steps of initiating a communication with the device under test and receiving a transmission frame from the device under test with a header portion comprising a specific transmission rate information. It also comprises analyzing the header portion of the transmission frame in order to determine whether the device under test is transmitting with the specific transmission rate information.

A method for increasing a reliability of a transducer is provided. The transducer has a first and a second IC, wherein the two ICs each have substantially the same monolithically integrated circuit components with one sensor apiece, and a signal contact for bidirectional data transmission. A reference contact on each of the two ICs is connected to or disconnected from the signal contact by a controllable switch, and a signal generated as a function of the physical quantity sensed by the relevant sensor is applied to the signal contact. The two ICs are integrated into a common IC package, and a supply voltage contact of the first IC is connected to a first package contact, and the first package contact is connected to a first terminal of a control unit, and the supply voltage contact of the second IC is connected to a second package contact.

The present disclosure provides a method of testing a single device under test (DUT) through multiple cores in parallel, which includes steps as follows. The test quantity of the DUT is calculated; the test quantity of the DUT is evenly allocated to to a plurality of test cores, so as to control a period of testing the DUT through the test cores in parallel.

A calibrated test and measurement cable for connecting one or more devices under test and a test and measurement instrument, including a first port structured to electrically connect to a first signal lane, a second port structured to electrically connect to a second signal lane, a third port structured to electrically connect to a test and measurement instrument, and a multiplexer configured to switch between electrically connecting the first port to the third port and connected the second port to the third port. The first and second signal lanes can be included on the same device under test or different devices under test. An input can receive instructions to operate the multiplexer.

A measurement system is described. The measurement system includes a test-and-measurement (T&A) circuit and an error analysis circuit. The T&A circuit is configured to generate measurement data. The measurement data includes at least one of analysis data and configuration data. The analysis data is associated with an analysis of at least one input signal. The configuration data is associated with at least one of a physical measurement setup of the measurement system and measurement settings of the measurement system. The T&A circuit further is configured to generate a graphic representation of the measurement data. The error analysis circuit is configured to identify errors or anomalies associated with the measurement data based on the graphic representation. Further, a measurement method is described.

An integrated circuit with functional circuitry and testing circuitry, the testing circuitry having a state machine operable in a plurality of different states. The integrated circuit also has a pin for receiving a signal, wherein the state machine is operable to transition between states in response to a change in level of the signal. Circuitry couples the signal of the pin, in a first level, to the state machine in a first time period for causing the state machine to enter a predetermined state, and circuitry maintains the signal in the first level to the state machine in a second time period for maintaining the state machine in the predetermined state. Also during the second time period, circuitry couples data received at the pin to a destination circuit other than the state machine, wherein the destination circuit is operable to perform plural successive scan tests using data from the pin without a power on reset of the functional circuitry.