A test and measurement system includes a primary instrument having an input for receiving a test signal for measurement or analysis from a Device Under Test (DUT) and generating a test waveform from the test signal, and a duplicator for sending a copy of the test waveform to one or more secondary instruments. The one or more secondary instruments are each structured to access the copy of the test signal for analysis, and each of the one or more secondary instruments includes a receiver structured to receive a command related to measurement or analysis of the copy of the test waveform, one or more processes for executing the received command, and an output for sending results of the executed command to be displayed on a user interface that is separate from any user interface of the one or more secondary instruments.

A force-sense system can provide signals to, or receive signals from, a device under test (DUT) at a first DUT node. The system can include output buffer circuitry configured to provide a DUT signal to the DUT in response to a force control signal at a buffer control node, and controller circuitry configured to provide the force control signal at the buffer control node. The system can include bypass circuitry configured to selectively bypass the controller circuitry and provide an auxiliary control signal at the buffer control node. The auxiliary control signal can be used for system calibration. In an example, an external calibration circuit can provide the auxiliary control signal in response to information received from the DUT.

A test board configured to test a device under test includes: a connection region including first and second connection terminals for contacting the device under test; and a first surface mount device located adjacent to the connection region, wherein the first connection terminal is configured to be electrically connected to a first voltage regulator of the device under test, wherein the second connection terminal is configured to be electrically connected to a second voltage regulator of the device under test, and wherein the first surface mount device is configured to be electrically connected to each of the first and second connection terminals.

A status of one or more components of a battery monitor circuit can be evaluated, such as to validate operation of the monitor circuit. In an example, a battery monitor circuit can be evaluated by providing a first test signal to a battery voltage measurement circuit that is coupled to a battery. A first analog-to-digital converter (ADC) circuit can be configured to receive a first voltage signal from the battery voltage measurement circuit in response to the first test signal. A processor circuit can be configured to validate the first ADC circuit by evaluating a correspondence between the first test signal and the received first voltage signal. One or more other ADC circuits in the battery monitor circuit can be validated by cross-checking measurement results with information from the first ADC circuit.

A Switching Mode Interposer (SMI) arrangement for boundary-scan testing of a Multi-Chip Module having a System-On-Chip, a Microprocessor Control Unit, and multiple chiplets-based devices including central processing units, graphical processing units, and/or memory devices disposed on a two-tiered interposer-substrate system. The SMI includes (a) a twin Test Access Port connected to a JTAG controller and configured to transmit test data in one direction (TAP-X) and an opposite direction (TAP-Y) along an Inter-Integrated Circuit (I2C) bus connected with the SOC, the MCU and the multiple devices, the test data being formatted according to IEEE 1149.1 or IEEE 1149.7 standard; and (b) a Mux/DeMux switch connected to the twin TAP and the I2C bus and responsive to the SOC or the MCU for selective switching of the test data along either the TAP-X or TAP-Y direction to a predetermined port associated with one of the multiple devices.

An extended joint test action group based controller and a method of use allows easier testing of integrated circuits by reducing the power dissipation of an IC. The extended joint test action group (JTAG) controller tests internal storage elements that form digital units in an integrated circuit (IC) use a design for testing scan infrastructure on the IC, wherein the JTAG controller is extended by an overall reset generator for all digital units of the IC, and a finite state machine controls the overall reset generator. In reset mode the JTAG controller stops the at least one clock module in supplying the digital units that should be reset. It then sets all scan chains in test mode and switches the input multiplexers into reset mode; and then controls the number of shift clock cycles for shifting in the reset value to the flip-flops in the scan chain, respectively.

A method for detecting error on an input/output (IO) pin of an integrated circuit includes using the input/output pin of the integrated circuit in a first mode by receiving or sending a first value as analog data or digital data. The input/output pin is toggled in a test mode after each instance of using the input/output pin in the first mode. The test mode includes providing a second value disparate from the first value during a set time after using the input/output pin in the first mode, receiving back during the set time a resulting value based on providing the second value, measuring the resulting value, and identifying an error on the input/output pin of the integrated circuit based on the measured resulting value.

Systems and methods are disclosed for testing a device under test (DUT) by receiving a test pattern for a functional test, wherein the test pattern includes a test vector, an expected test result, and an expected power consumption; instructing the test system to run a repetitive loop using a selected functional test as the stimulus; at selected steps in the functional test, measuring power consumption of the DUT; and validating the DUT based on validating the test vector and the power consumption with one or more expected test result patterns and expected power consumption patterns.

An automated test equipment (ATE) apparatus comprising a tester processor operable to generate commands and data for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises an FPGA communicatively coupled to the tester processor, wherein the FPGA comprises routing logic operable to route signals associated with the commands and data in the FPGA based on a type of the DUT. Further, the ATE comprises a connector module communicatively coupled to the FPGA comprising a socket to which the DUT connects and further comprising circuitry for routing the signals to a set of pins on the DUT, wherein the set of pins are associated with a first type of DUT. The circuitry can support multiple different DUT types having a common form factor but different pinout assignments.

A method for testing DUT comprises receiving instructions from a system controller at a tester board, wherein the tester board comprises an FPGA and the tester processor are coupled to the system controller, and wherein the tester processor is operable to coordinate testing of a device under test (DUT). The method further comprises generating commands and data for testing the DUT and routing signals associated with the commands and the data in the FPGA based on a type of the DUT. Also, the method comprises transmitting the signals over lanes corresponding to a particular set of pins on the DUT, wherein the particular set of pins depend on the type of the DUT.