A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

A test device configured to test a device under test (DUT) performing an interface of a pulse amplitude modulation (PAM) operation includes a logic generation/determination device configured to generate multiple bits corresponding to a test pattern, first and second drivers configured to generate respective first and second non return to zero (NRZ) signals according to a logic state of respective first and second bits among the multiple bits and output the respective generated first and second NRZ signals via respective first and second channels. The first NRZ signal has a first high level or a first low level according to the logic state of the first bit, and the second NRZ signal has a second high level or a second low level according to the logic state of the second bit. The first and second high levels are different from each other.

According to one or more embodiments, the semiconductor integrated circuit device includes a pattern generator, a result comparator, and a control circuit. The pattern generator supplies input data to a device-under-test. The result comparator compares output data of the device-under-test with expected value data and outputs a test result signal. The control circuit controls the pattern generator and the result comparator. The device-under-test and the result comparator are commonly connected to a first clock line. The pattern generator and the control circuit are commonly connected to a second clock line different from the first clock line.

A system and method for performing speaker load diagnostics. A digital signal processor generates a diagnostic tone that is provided to the speaker. The diagnostic tone is generated using an oscillator internal to the digital signal processor. The digital signal processor receives current and voltage data from the speaker based on the diagnostic tone, and processes the current and voltage data to determine whether a fault condition exists in the speaker.

A ground fault detection circuit can include a band-pass filter that can have a first node and a second node that can be coupled to an earth ground. The first node can be coupled to a local ground of an automatic test equipment (ATE) system for an electrical device that can be coupled via at least one wire to the ATE. The band-pass filter can be configured to pass and amplify a test current signal established at the first node in response to a coupling of one of a conductor of the at least one wire carrying the test current signal to the local ground, and a conductive element of the electrical device carrying the test current signal to the local ground. A fault alert signal can be provided to provide an indication of ground fault based on a comparison of the amplified test current signal.

A new test system includes a programmed device having an input port for receiving a signal for testing or measuring on the programmed device, and a reprogrammable test accessory having an output coupled to the input port of the programmed device. The reprogrammable test accessory further includes a test port structured to accept one or more test signals from a Device Under Test (DUT), and a reprogrammable processor. The reprogrammable processor may further include reprogrammable standards and protocols, reprogrammable triggers and margin detection, reprogrammable link training, reprogrammable handshaking, and reprogrammable setup and control facilities for either or both of the DUT and the programmed device.

The present disclosure discloses a method and an apparatus for testing an artificial intelligence chip test, a device and a storage medium, and relates to the field of artificial intelligence. The specific implementation solution is: the target artificial intelligence chip has multiple same arithmetic units, the method includes: obtaining scale information of the target artificial intelligence chip; determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information; dividing all the arithmetic units into multiple same arithmetic unit arrays, and performing a DFT test on the arithmetic unit arrays, respectively, if it is determined that the test condition of the arithmetic unit array level is satisfied; performing the DFT test on the arithmetic units, respectively, if it is not determined that the test condition of the arithmetic unit array level is not satisfied.

Embodiments of the present disclosure provide a test method and apparatus for a control chip, and an electronic device, which relate to the field of semiconductor device test technologies. The control chip includes a built-in self-test BIST circuit. The method is performed by the BIST circuit. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Provided is an apparatus including a generating section that generates an altered test candidate obtained by adding an alteration shortening an execution time of a test to a target test for testing a device under test; a test processing section that causes a test apparatus to perform the altered test candidate on the device under test; and a comparing section that compares an altered test result of the device under test resulting from the altered test candidate to a target test result of the device under test resulting from the target test; and a judging section that judges whether the target test can be replaced by the altered test candidate, based on the comparison result of the comparing section.

A power consumption measurement assembly includes: at least two sampling modules respectively connected to a circuit to be measured in series; a gating module configured to gate one of the at least two sampling modules; an amplifying module configured to acquire and amplify a voltage signal across the gated sampling module; and a processing module connected to the gating module and the amplifying module and configured to: control and adjust the gated sampling module and an amplification of the amplifying module, calculate a power consumption value based on the amplified voltage signal and transmit the power consumption value.