Methods and systems of detecting chip degradation are described. A processor may execute a test on a device at a first time, where the test includes executable instructions for the device to execute a task under specific conditions relating to a performance attribute. The processor may receive performance data indicating a set of outcomes from the task executed by the device during the test. The processor may determine a first value of a parameter of the performance attribute based on the identified subset. The processor may compare the first value with a second value of the parameter of the performance attribute. The second value is based on an execution of the test on the device at a second time. The processor may determine a degradation status of the device based on the comparison of the first value with the second value.

A system and method for performing speaker load diagnostics. A digital signal processor generates a diagnostic tone that is provided to the speaker. The diagnostic tone is generated using an oscillator internal to the digital signal processor. The digital signal processor receives current and voltage data from the speaker based on the diagnostic tone, and processes the current and voltage data to determine whether a fault condition exists in the speaker.

Provided is an apparatus including a generating section that generates an altered test candidate obtained by adding an alteration shortening an execution time of a test to a target test for testing a device under test; a test processing section that causes a test apparatus to perform the altered test candidate on the device under test; and a comparing section that compares an altered test result of the device under test resulting from the altered test candidate to a target test result of the device under test resulting from the target test; and a judging section that judges whether the target test can be replaced by the altered test candidate, based on the comparison result of the comparing section.

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

A semiconductor device, a semiconductor system, and a control method of a semiconductor device are capable of accurately monitoring the lowest operating voltage of a circuit to be monitored. According to one embodiment, a monitor unit of a semiconductor system includes a voltage monitor that is driven by a second power supply voltage different from a first power supply voltage supplied to an internal circuit that is a circuit to be monitored and monitors the first power supply voltage, and a delay monitor that is driven by the first power supply voltage and monitors the signal propagation period of time of a critical path in the internal circuit.

A semiconductor device, a semiconductor system, and a control method of a semiconductor device are capable of accurately monitoring the lowest operating voltage of a circuit to be monitored. According to one embodiment, a monitor unit of a semiconductor system includes a voltage monitor that is driven by a second power supply voltage different from a first power supply voltage supplied to an internal circuit that is a circuit to be monitored and monitors the first power supply voltage, and a delay monitor that is driven by the first power supply voltage and monitors the signal propagation period of time of a critical path in the internal circuit.

A determination device includes an estimation circuit and a determination circuit. The estimation circuit generates estimation data by estimating input data in the n-th cycle based on the input data in cycles prior to the n-th cycle and a first generator polynomial. The determination circuit determines whether the input data and the estimation data match. The first generator polynomial is an arithmetic expression that sets the estimation data in the n-th cycle to an inverted value of the input data in (n?1)-th cycle if a logical sum of all the input data in a first period corresponding to a preset number of cycles prior to the n-th cycle is 0 or a logical product of all the input data in a second period corresponding to the preset number of cycles prior to the n-th cycle is 1, and sets the estimation data in the n-th cycle to the same value as the input data in the (n?1)-th cycle if the logical sum is not 0 and the logical product is not 1.

A self-diagnosis circuit (BST1) configured to diagnose a fault detection circuit (20) including a first comparator (CMP1) configured to be fed with a voltage based on a fault sensing target voltage (Vo1) and a first reference voltage (Vref1) includes a voltage switch circuit (50) configured to switch the level of a voltage based on a second reference voltage (Vref2) and output the resulting voltage, a first path switch circuit (51) configured to switch between a path through which the voltage output from the voltage switch circuit is fed to the first comparator and a path through which the voltage based on the fault sensing target voltage is fed to the first comparator, and a control circuit (15) configured to control the voltage switch circuit and the path switch circuit.

A method and an apparatus for integrated circuit testing are provided. The method includes: operating a tester to perform a qualitative testing on devices in the integrated circuit by following electrical addresses of the devices, and to introduce an original verification pattern during the qualitative testing, such that a verification pattern corresponding to the original verification pattern can be converted from a raw data of a result of the qualitative testing; converting the raw data to a test graph presented by physical addresses, by using pre-determined scramble equations; and identifying portions of the verification pattern appeared in the test graph and comparing the portions of the verification pattern with corresponding portions of the original verification pattern by pattern recognition, and correcting the pre-determined scramble equations according to comparison result.

A method and an apparatus for integrated circuit testing are provided. The method includes: operating a tester to perform a qualitative testing on devices in the integrated circuit by following electrical addresses of the devices, and to introduce an original verification pattern during the qualitative testing, such that a verification pattern corresponding to the original verification pattern can be converted from a raw data of a result of the qualitative testing; converting the raw data to a test graph presented by physical addresses, by using pre-determined scramble equations; and identifying portions of the verification pattern appeared in the test graph and comparing the portions of the verification pattern with corresponding portions of the original verification pattern by pattern recognition, and correcting the pre-determined scramble equations according to comparison result.