A method, and forming an associated system, for testing semiconductor devices. Driver channels are provided, each driver channel connected to a storage device via a bus and connected to a respective semiconductor device. Each driver channel includes: a first voltage driver connected to the respective semiconductor device and having a first input for the respective semiconductor device, a second voltage driver connected to the respective semiconductor device and having a second input for the respective semiconductor device, first and second sets of optical switches in the first and second voltage driver respectively, and a microcontroller. All connections between the respective semiconductor device and both the first and second voltage drivers, in response to all optical switches of the first and second set of optical switches being closed. The semiconductor devices are tested, using the driver channels and the test parameters. The test results are provided to the storage device.

According to one or more embodiments, the semiconductor integrated circuit device includes a pattern generator, a result comparator, and a control circuit. The pattern generator supplies input data to a device-under-test. The result comparator compares output data of the device-under-test with expected value data and outputs a test result signal. The control circuit controls the pattern generator and the result comparator. The device-under-test and the result comparator are commonly connected to a first clock line. The pattern generator and the control circuit are commonly connected to a second clock line different from the first clock line.

An apparatus comprises a first semiconductor chip comprising a first communication controller to receive first debug data from a second semiconductor chip; a memory to store the first debug data from the second semiconductor chip and second debug data of the first semiconductor chip; and a second communication controller to transmit the first debug data from the second semiconductor chip and the second debug data of the first semiconductor chip to an output port of the first semiconductor chip.

According to one or more embodiments, the semiconductor integrated circuit device includes a pattern generator, a result comparator, and a control circuit. The pattern generator supplies input data to a device-under-test. The result comparator compares output data of the device-under-test with expected value data and outputs a test result signal. The control circuit controls the pattern generator and the result comparator. The device-under-test and the result comparator are commonly connected to a first clock line. The pattern generator and the control circuit are commonly connected to a second clock line different from the first clock line.

This document describes techniques and systems for leakage screening based on power prediction. In particular, the described systems and techniques estimate, during a silicon manufacturing process, use-case power (e.g., low power, ambient power, high power, gaming power) to apply leakage screening for apart (e.g., a chip package). In some aspects, measurable silicon parameters (e.g., leakage values, bin values, processor sensor values) may be used for use-case power prediction. Using the described techniques, a maximum allowable predicted use-case power can be determined and used for leakage screening regardless of an individual rail leakage or voltage bin assignment.

A method for detecting errors of a first field-programmable gate array (FPGA) program includes: receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.

A waveform data acquisition module includes an A/D converter that converts an electrical signal relating to a DUT into a digital signal, and a first memory unit that stores waveform data configured as a digital signal sequence. A function test module includes a test unit and a second memory unit. A higher-level controller instructs the waveform data acquisition module to start data sampling, and holds the time point thereof. Furthermore, the higher-level controller instructs the function test module to start to execute a pattern program, and records the time point thereof. The first memory unit records the time point at which the data sampling is started. The higher-level controller records the time point at which the execution of the pattern program is started.

A measurement system is described. The measurement system includes a test-and-measurement (T&A) circuit and an error analysis circuit. The T&A circuit is configured to generate measurement data. The measurement data includes at least one of analysis data and configuration data. The analysis data is associated with an analysis of at least one input signal. The configuration data is associated with at least one of a physical measurement setup of the measurement system and measurement settings of the measurement system. The T&A circuit further is configured to generate a graphic representation of the measurement data. The error analysis circuit is configured to identify errors or anomalies associated with the measurement data based on the graphic representation. Further, a measurement method is described.

The present invention provides a measuring device (1, 11) for measuring signals (2, 12), the measuring device (1, 11) comprising a data memory (4, 14) configured to store device data (5, 15) for the measuring device (1, 11), and a data interface (6, 16) connected to the data memory (4, 14) and configured to read the device data (5, 15) from the data memory (4, 14) and output at least a part of the read device data (5, 15) to an external memory device (7, 17) in a storage mode and to read device data (5, 15) from the external memory device (7, 17) and store the read device data (5, 15) in the data memory (4, 14) in a recovery mode. The present invention further provides a corresponding method for such a measuring device (1, 11).

Disclosed in some examples are methods, systems, memory devices, machine readable mediums configured to intentionally degrade NAND performance when a value of a NAND health metric indicates a potential for failure to encourage users to replace or backup their devices before data loss occurs. For example, the system may track a NAND health metric and when that metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may be more effective than a warning to effect device backup or replacement.