An error rate measuring apparatus includes a data transmission unit that transmits a test signal of a known pattern and a parameter value defined by a communication standard to a device under test, and a bit error measurement unit that measures a bit error of a signal transmitted from the device under test. The data transmission unit sequentially changes the parameter value and transmits the parameter value to the device under test. The bit error measurement unit measures a bit error of a signal transmitted from the device under test corresponding to the parameter value. The error rate measuring apparatus further includes a discrimination unit that discriminates a parameter value at which the number of bit errors is the least in a measurement result of the bit error measurement unit, as an optimum value of emphasis of an output waveform of the device under test.

A method for determining the propagation delay of each path in an integrated circuit is provided herein. The method includes determining, in a worst-based mode, whether a propagation delay of a selected path exceeds a timing requirement; determining, in a path-based mode, whether the propagation delay of a selected path exceeds the timing requirement; and when the selected path exceeds the timing requirement in the path-based mode, lowering the cell delay of each cell in the selected path.

Embodiments described herein generally relate to measuring and evaluating a test signal generated by a device under test (DUT). In particular, the test signal generated by the DUT may be compared to a reference signal and scored based on the comparison. For example, a method may include: capturing a test signal from a device under test; splicing the test signal into a plurality of test audio files based on a plurality of frequency bins; at each frequency bin, comparing each of the plurality of test audio files to a corresponding reference audio file from among a plurality of reference audio files, the plurality of reference audio files being associated with a reference signal; and calculating a performance score of the device under test based on the comparisons.

Embodiments of the present invention provide systems and methods for automatically performing TDR calibration to compensate for the time delay of a signal carried over a transmission environment (e.g., cable or other electrical path) used during DUT testing. A signal provider generates a signal along a signal path, and a circuit comprising a capacitor coupled to the signal provider and a diode coupled to the capacitor receives the signal periodically. A measurement unit coupled to the capacitor and the diode measures a voltage at the capacitor to determine a signal characteristic value of the signal along the signal path. The signal characteristic value is used to determine the electrical length (delay) of the transmission environment. TDR calibration is performed using the electrical length to compensate for the time delay/reflections over the transmission environment during testing. Advantageously, embodiments do not use a comparator circuit or a receiver circuit, and therefore can perform TDR calibration without significantly reducing the bandwidth of the testing equipment.

A computer system may determine a first set of output values for a set of test paths at a first time. Each output value may correspond to a test path in the set of test paths. The computer system may then determine a second set of output values at a second time. Each output value in the second set of output values may have an associated output value in the first set of output values. The computer system may then determine whether degradation of the semiconductor chip has occurred by comparing the first set of output values to the second set of output values.

A chip health monitor includes a processor configured to operate as a state machine based on instructions stored in a storage device. The state machine is configured to exercise a signal path in a chip in response to a condition and determine presence of an error in the signal path based on results from the exercise. The state machine is configured to compensate for the error by changing at least one operational parameter of the chip.

Systems, methods, and computer readable medium described herein relate to techniques for characterizing and/or anomaly detection in integrated circuits such as, but not limited to, field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). In one example aspect of certain example embodiments, a fully digital technique relies on the pulse width of signals propagated through a path under test. In another example aspect, the re-configurability of the integrated circuit is leveraged to combine the pulse propagation technique with a delay characterization technique to yield better detection of certain type of Trojans and the like. Another example aspect provides for running the test through reconfigurable path segments in order to isolate and identify anomalous circuit elements. Yet another example aspect provides for performing the characterization and anomaly detection without requiring golden references and the like.

Embodiments described herein generally relate to measuring and evaluating a test signal generated by a device under test (DUT). In particular, the test signal generated by the DUT may be compared to a reference signal and scored based on the comparison. For example, a method may include: capturing a test signal from a device under test; splicing the test signal into a plurality of test audio files based on a plurality of frequency bins; at each frequency bin, comparing each of the plurality of test audio files to a corresponding reference audio file from among a plurality of reference audio files, the plurality of reference audio files being associated with a reference signal; and calculating a performance score of the device under test based on the comparisons.

The invention concerns devices and methods for calibrating an Automated Test Equipment for automated testing of a Device Under Test. The method includes providing two digital channel signals by two different channels of the Automated Test Equipment, wherein the digital channel signals include an identical or a complementary pattern with respect to their edges. The method further includes sum-combining or difference-combining the two digital channel signals in order to obtain a combined residual signal. The step of combining is performed such that combining provides a combined residual signal without a time-variant component if the two digital channel signals have a predetermined time shift or a predetermined phase shift relative to each other, or such that the combined residual signal includes a time variant component if the two digital channel signals have a time shift different from the predetermined time shift or a phase shift different from the predetermined phase shift.

A method and associated systems for using direct sums and invariance groups to optimize the testing of partially symmetric quantum-logic circuits is disclosed. A test system receives information that describes the architecture of a quantum-logic circuit to be tested. The system uses this information to organize the circuit's inputs into two or more mutually exclusive subsets of inputs. The system computes a direct sum of a set of groups associated with the subsets in order to generate an invariance group that contains one or more invariant permutations of the circuit's inputs. These invariant permutations can be used to reduce the number of tests required to fully verify the circuit for all possible input vectors. Once one specific input vector has been verified, there is no need to test other vectors that can be generated by performing any one of the invariant permutations upon the previously verified vector.