Provided are a display substrate, a display panel and a display device. The display substrate includes a display area, a bezel area and multiple first signal lines. The bezel area includes a bonding area, the bonding area includes a first area and a second area, the first area includes first pads, and the second area includes second pads. The first signal lines are electrically connected to the first pads. Each of at least part of the first signal lines extends between respective two adjacent first pads. The second pads are dummy pads, or part of the second pads are electrically connected to a second signal line. The bonding area further includes multiple dummy traces, and at least part area of a dummy trace is disposed between two adjacent first pads, and/or between two adjacent second pads, and/or between a first pad and a second pad adjacent to each other.

An electronic device has a display screen and a driver chip disposed on a driver area of the display screen. A fan-out area of the display screen has interconnects configured to provide electrical accesses to display elements of the display area. The driver chip includes a first edge, a second edge, and a row of electronic pads proximate to the first edge. The electronic pads have a first subset of end pads at a first end of the first row, a second subset of end pads at a second opposite end of the first row, and a subset of intermediate pads located between the first subset and second subset of end pads. The first subset of end pads physically contact a first subset of interconnects from the first edge, and the subset of intermediate pads physically contact a second subset of interconnects from the one or more second edges.

An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area has interconnects providing electrical accesses to display elements of the display area. The device has a driver chip disposed on the driver area. The driver chip includes a first edge adjacent to the display area and multiple pad groups, each pad group including a respective row of electronic pads that is (i) arranged substantially in parallel with the first edge and (ii) electrically coupled to a respective subset of display elements via respective interconnects routed on a respective region of the fan-out area. The pad groups include a first pad group and a second pad group. The first and second pad groups have two different distances from the first edge and correspond to two different subsets of interconnects routed on two non-overlapping regions of the fan-out area.

A display device includes a display panel including a side surface; on the side surface of the display panel: a pad through which an electrical signal is provided to the display panel from outside thereof; and an auxiliary layer in a same layer as the pad and spaced apart from the pad along a thickness direction of the display panel; and a circuit member facing the side surface of the display panel and coupled to both the pad and the auxiliary layer.

A display panel includes: a first substrate; and a pad including a first conductive layer and a first coupling part. The first conductive layer is disposed on the first substrate, and the first coupling part includes a first pattern protruding from the first conductive layer and having a bent shape.

An electronic device has a display screen and a driver chip disposed on a driver area of the display screen. A fan-out area of the display screen has interconnects configured to provide electrical accesses to display elements of the display area. The driver chip includes a first edge, a second edge, and a row of electronic pads proximate to the first edge. The electronic pads have a first subset of end pads at a first end of the first row, a second subset of end pads at a second opposite end of the first row, and a subset of intermediate pads located between the first subset and second subset of end pads. The first subset of end pads physically contact a first subset of interconnects from the first edge, and the subset of intermediate pads physically contact a second subset of interconnects from the one or more second edges.

A display device including a lower substrate, a display structure, pad electrodes, and a driver integrated circuit. The lower substrate has a display area and a pad area. The display structure is disposed in the display area on the lower substrate. The pad electrodes are disposed in the pad area on the lower substrate while being spaced apart from each other in a first direction. The driver integrated circuit is spaced apart from the pad electrodes in the second direction in the pad area on the lower substrate, and includes a circuit portion and a first blocking portion spaced apart from the circuit portion in a second direction perpendicular to the first direction.

A display device and a screen anti-peeping device are provided. The display device includes a display panel and the screen anti-peeping device. The display panel includes at least one bonding area, wherein the bonding area is configured to be coupled to an outer lead. The screen anti-peeping device overlaps with the display panel and includes a plurality of electrode sets, wherein each of the electrode sets includes a first electrode and a second electrode. At least one of the electrode sets is selected to be coupled to at least one control lead, and the selected electrode set is misaligned with the bonding area.

An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.

An active matrix substrate includes a glass substrate 26, a plurality of pixel electrodes 40 arrayed in a matrix, a plurality of TFTs 43, a plurality of common electrodes 42, a terminal group 60 provided at one end of a Y-axis direction on top of the glass substrate 26 and constituted by a plurality of terminals 61 and 62 placed along an X-axis direction, wires 71 that electrically connect the terminals 61 to the TFTs 43, and wires 72 that electrically connect the terminals 62 to the common electrodes 42. The terminal group 60 includes a center terminal group 64, constituted by a plurality of the first terminals 61, that constitutes a center portion of the terminal group 60 in the X-axis direction, and end terminal groups 65L and 65R, each constituted by a plurality of the first terminals and a plurality of the second terminals, that constitute both side portions, respectively, of the terminal group 60 in the X-axis direction and in each of which the second terminals 62 are each disposed between two of the first terminals 61 adjacent to each other.