A method of manufacturing an array substrate, includes: providing a substrate; forming a gate conductive layer including at least one first alignment mark; forming a source-drain conductive thin film; aligning a first mask and the substrate on which the gate conductive layer and the source-drain conductive thin film have been formed according to the at least one first alignment mark; patterning the source-drain conductive thin film by using the first mask to form at least one second alignment mark to obtain a source-drain conductive layer; forming a black matrix thin film; aligning a second mask and the substrate on which the gate conductive layer, the source-drain conductive layer and the black matrix thin film have been formed according to the at least one second alignment mark; patterning the black matrix thin film by using the second mask to form a black matrix; and forming a color filter layer.

The present invention is about display technology. A display panel and a display device are provided. The display panel includes: a substrate layer; a data line arranged on the substrate layer; a color resist layer which is arranged on the substrate layer and located at two sides of the data line, and includes grooves which are located at least at one side of the data line; a shielding layer arranged on the color resist layer and arranged over the data line; a pixel electrode layer arranged over the shielding layer; and a passivation layer arranged between the shielding layer and the pixel electrode layer and covering the shielding layer and the color resist layer.

An array substrate, a manufacturing method thereof and a display device are provided. The array substrate includes: a base substrate; a first electrode located on the base substrate and including a pad portion, the pad portion including a first surface and a second surface, the second surface being closer to the base substrate than the first surface; a first insulation layer located on the first electrode and including a first via hole; a second insulation layer located on the first insulation layer and including a second via hole; and a second electrode located on the second insulation layer; the second electrode is electrically connected with the first electrode at the pad portion through the first via hole and the second via hole, and an orthographic projection of the pad portion on the base substrate falls within an orthographic projection of the second via hole on the base substrate.

Embodiments of this application disclose a display panel. A primary pixel electrode is disposed inside a primary pixel region, and a sub-pixel electrode is disposed inside a sub-pixel region. First shading strips and second shading strips are intersected to form a plurality of primary frame bodies. One primary frame body correspondingly encloses a circumferential side of one pixel region. A third shading strip is disposed inside the primary frame body and correspondingly disposed between the primary pixel region and the sub-pixel region. The third shading strip and the primary frame body define two sub-frame bodies, and a channel for making the two sub-frame bodies communicate is disposed on the third shading strip.

An array substrate and a display panel are disclosed. A common electrode layer on the array substrate includes a common electrode trunk and multiple common electrode branches. A pixel electrode layer includes multiple interconnected pixel electrode branches, each of which includes a branch body and a branch end connected therewith. The branch end includes a first side opposite to the common electrode trunk to form a first gap, and a second side and a third side respectively disposed opposite to the corresponding common electrode branches to form a second gap and a third gap. A fourth gap is formed between the branch body and the common electrode branch. Of the first, the second and the third gaps, the width value corresponding to at least one gap is smaller than the width of the fourth gap.

This application provides a pixel structure and a display device thereof. The pixel structure includes: a plurality of pixel regions, each of the pixel regions including a plurality of sub-pixels, the plurality of sub-pixels of each pixel area including the first sub-pixel, and the first sub-pixel is configured at the center of each pixel area; sub-pixels of the remaining colors in the plurality of sub-pixels of each pixel area are centered on the first sub-pixel, configured on both sides of the first sub-pixel; and a color filter layer including a plurality of color resist layers, where the plurality of color resist layers are arranged corresponding to positions and colors of the plurality of pixel regions.

This application discloses a method for manufacturing a display panel, a display panel, and a display device. The display panel has a display area and a peripheral area. The display panel includes a first substrate, a second substrate, a plurality of pixel elements, a plurality of data lines and scanning lines, and a plurality of color filters. The first substrate includes a first shading layer, the first shading layer being formed between two neighboring pixel elements to block the data lines or the scanning lines. The display area includes an opening area and a non-opening area, and the first shading layer is arranged only in the non-opening area. The second substrate includes a second shading layer arranged corresponding to the first shading layer. Each of the data lines and the scanning lines is blocked by at least one of the first shading layer and the second shading layer.

An electronic device including a first substrate, a semiconductor layer, a second substrate and a color filter is disclosed. The first substrate has a peripheral region. The semiconductor layer is disposed on the first substrate in the peripheral region. The second substrate is opposite to the first substrate. The color filter is disposed between the first substrate and the second substrate and in the peripheral region of the first substrate, and the color filter overlaps the semiconductor layer.

A pixel array substrate including a substrate, multiple insulation patterns, multiple signal lines, and multiple pixel structures is provided. The insulation patterns are disposed on the substrate, and each has at least one recess structure. The signal lines are respectively disposed on the insulation patterns and are respectively filled in the at least one recess structure of one of the insulation patterns. The pixel structures are disposed on the substrate and are electrically connected to the signal lines. A pixel array substrate further including multiple conductive patterns is also disposed.

Provided are a display panel and a display device. The display panel includes multiple data lines and multiple scanning lines. The multiple data lines intersect with the multiple scanning lines to define multiple pixel units arranged in an array, and the data lines are insulated from the scanning lines; and pixel electrodes of pixel units that are among the multiple pixel units and in at least portion of the array include multiple first branch electrodes arranged in parallel; along a direction of the multiple scanning lines, each of the multiple first branch electrodes includes multiple first branch electrode segments connected sequentially; and an included angle between two adjacently connected first branch electrode segments of the multiple first branch electrode segments is less than 180°.