A display panel includes an array substrate, a color filter substrate, and a liquid crystal layer. The array substrate includes a scan line and a data line; a pixel electrode disposed corresponding to a pixel area; a first thin film transistor configured to electrically connect the pixel electrode to the scan line and the data line; an auxiliary electrode disposed on a same layer as the pixel electrode and arranged around the pixel electrode; and a second thin film transistor configured to electrically connect the auxiliary electrode to the first thin film transistor. Potential received by the pixel electrode and potential received by the auxiliary electrode have a difference.

A display device includes a substrate, a scan line disposed on the substrate, a storage line parallel to the scan line and a data line intersecting the scan line and the storage line. First and second transistors are electrically connected to the scan line and the data line. A first pixel electrode is disposed on the first transistor and includes a first stem portion, a first contact portion and a first branch portion. The first branch portion electrically connects the first contact portion to the first stem portion, a second pixel electrode is disposed on the second transistor and includes a second stem portion, a second contact portion and a second branch portion. The second branch portion electrically connects the second contact portion to the second stem portion. A first pattern is disposed between the substrate and the second pixel electrode. The first pattern overlaps the second branch portion.

A flat panel display having an improved picture quality is disclosed. In one embodiment, a first pixel electrode and a second pixel electrode are formed in each subpixel area. The electrodes enclose an open space (gap) such that their outer boundary has a substantially rectangular shape. The flat panel display may also include a capacitance electrode coupled to the second pixel electrode to form a coupling capacitor. In use, the coupling capacitor operates such that a magnitude of a voltage applied to the first pixel electrode is lower than an applied data voltage, and a magnitude of a voltage applied to the second pixel electrode is higher than an applied voltage. The different voltages operate such that a tilt direction of LC molecules disposed above the first pixel electrode differs from a tilt direction of LC molecules disposed above the second pixel electrode.

A liquid crystal display apparatus switches modes from a normal display mode to a stop preparation mode when a main power source voltage drops. In the display mode, a gate drive circuit sequentially applies a first gate-on pulse to gate bus lines so as to select pixel rows sequentially, and applies a second gate-on pulse to buffer capacitor scanning lines, each of which is associated with a pixel row selected by the first gate-on pulse, during a period that does not overlap a period during which the first gate-on pulse is applied, and a source drive circuit applies a display signal voltage to source bus lines. In the stop preparation mode, the gate drive circuit sequentially applies the first gate-on pulse to the gate bus lines so as to select the pixel rows sequentially, and applies the second gate-on pulse to the buffer capacitor scanning lines, each of which is associated with the pixel row selected by the first gate-on pulse, during a period that at least partially overlaps a period during which the first gate-on pulse is applied, and the source drive circuit applies 0 V to the source bus lines.

To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

A display device includes a display panel including pixels, each including first, second, and third color pixels; a gate driver and a data driver connected to the pixel through a scan line and a data line, respectively. Each of the first, second, and third color pixels includes a color pixel electrode and a first transistor having a first electrode connected to the data line, a second electrode connected to the color pixel electrode, and a gate electrode connected to the scan line. A voltage distribution line is disposed to overlap the color pixel electrode of the third color pixel in a thickness direction extending in the second direction. A width of the second electrode of the first transistor of the third color pixel is greater than a width of that of each of the first and second color pixels in the first direction.

An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

The present disclosure provides an array substrate and a display panel including the same. The array substrate includes a plurality of pixel units. Each of the pixel units includes a main pixel electrode, a sub-pixel electrode, a first thin film transistor (TFT) electrically connected to the sub-pixel electrode, a second TFT electrically connected to the first TFT, and a third TFT electrically connected to the main pixel electrode. The first TFT includes a first channel and a first semiconductor layer. The first channel includes two or more subchannels. The first semiconductor layer includes two or more semiconductor sublayers. Each of the semiconductor sublayers is disposed in a corresponding subchannel.

A display device capable of improving image quality is provided. The display device includes a first circuit, a pixel, and a wiring. The first circuit has a function of supplying data to the wiring and a function of making the wiring floating to hold the data. The pixel has a function of taking in the data twice from the wiring and performing addition. The pixel can perform the first writing of the data in a period during which the data is supplied to the wiring, and can perform the second writing of the data in a period during which the data is held in the wiring. Therefore, by one time of data charging to a source line, a data potential larger than or equal to an output voltage of a source driver can be supplied to a display element.

A pixel structure includes a data line, a scan line, a common signal line, a first switching element, a second switching element, a first pixel electrode, and a second pixel electrode. The first switching element is electrically connected to the scan line and the data line. The second switching element is electrically connected to the scan line and the common signal line. The first pixel electrode is electrically connected to the first switching element. The second pixel electrode is electrically connected to the second switching element. The second pixel electrode surrounds the first pixel electrode.