Provided is a liquid crystal display capable of reducing a texture by increasing a liquid crystal control ability. The liquid crystal display includes a first electrode and a second electrode facing each other with a liquid crystal layer therebetween. The first electrode includes a horizontal extension forming a boundary between adjacent subregions and a vertical extension connected to the horizontal extension, and the horizontal extension includes a portion which has a largest width at a position proximate to the vertical extension, and which has a smaller width at a position farther from the vertical extension.

A liquid crystal display device with a novel structure is provided. Each pixel includes a first circuit for holding a high level (or low level) potential and a second circuit for holding a low level (or high level) potential. A semiconductor layer of a transistor included in each of the first and second circuits is an oxide semiconductor layer. The second circuit is reset when being supplied with the high level potential. Whether the high level potential held in the second circuit changes is controlled by a data voltage supplied to the first circuit. The potential held in the first circuit and the potential held in the second circuit are respectively supplied to a first transistor and a second transistor.

A liquid crystal display device includes a lower electrode and a plurality of upper electrodes opposed to the lower electrode formed in the first substrate. At least one first upper electrode and at least one second upper electrode of the plurality of upper electrodes are formed in each of the plurality of pixels. Each of the first upper electrodes has a plurality of slits that extend in a first direction, each of the second upper electrodes has a plurality of slits that extend in a second direction which is different from the first direction, and the first and second upper electrodes are electrically isolated from each other.

A liquid crystal display includes a first display substrate including a plurality of pixel electrodes corresponding to a plurality of pixels, respectively, a second display substrate disposed opposite to the first display substrate; and a liquid crystal layer disposed between the first and second display substrates, where each of the pixel electrodes includes first and second subpixel electrodes, which are disposed near each other in a first direction and each include a plurality of minute branches, the first subpixel electrode is divided into a plurality of first-subpixel areas including a first first-subpixel area, in which the minute branches extend in a first diagonal direction, and the second subpixel electrode includes a plurality of second-subpixel areas including a first second-subpixel area, which is disposed near the first first-subpixel area in the first direction and in which the minute branches extend in the first diagonal direction.

An object is to provide a display device that performs accurate display. A circuit is formed using a transistor that includes an oxide semiconductor and has a low off-state current. A precharge circuit or an inspection circuit is formed in addition to a pixel circuit. The off-state current is low because the oxide semiconductor is used. Thus, it is not likely that a signal or voltage is leaked in the precharge circuit or the inspection circuit to cause defective display. As a result, a display device that performs accurate display can be provided.

An array substrate, a manufacturing method therefor, and a display device are provided. The array substrate comprises multiple pixel units, where at least one of the pixel units comprises a first subpixel electrode and a second subpixel electrode, the first subpixel electrode is electrically connected to a first charging thin-film transistor, and the second subpixel electrode is electrically connected to a second charging thin-film transistor. In same one pixel unit, the charging capacity of the second charging thin-film transistor is greater than the charging capacity of the first charging thin-film transistor.

A transistor display panel including: a driving voltage line and a first electrode disposed on a substrate; a semiconductor overlapping the first electrode; and an electrode layer overlapping the semiconductor, the electrode layer including a drain electrode, a gate electrode, and a source electrode. The first electrode and the semiconductor are connected through the source electrode.

A display device includes: a substrate; a first thin film transistor unit disposed on the substrate and comprising a first active layer comprising a silicon layer, wherein the first active layer comprises a channel region, a source region and a drain region; a second thin film transistor unit disposed on the substrate and comprising a second active layer comprising a metal oxide layer; and a display medium disposed on the first thin film transistor unit and the second thin film transistor unit. Herein, a thickness of the silicon layer in the channel region is less than or equal to a thickness of the silicon layer in the source region.

A liquid crystal display device includes a first substrate spaced from a second substrate, a liquid crystal layer between the first and second substrates, a gate line, a data line, a first sub-pixel electrode, and a second sub-pixel electrode on the first substrate. The display device also includes a first switch and a second switch. The first switch is connected to the gate line, the data line, and the first sub-pixel electrode. The second switch is connected to the gate line, the data line, and the second sub-pixel electrode. The second switch includes a first gate electrode connected to the gate line and a second gate electrode not connected to the gate line.

A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel unit is connected to the pixel TFT through a hole bored in at least a protective insulation film formed of an inorganic insulating material and formed above a gate electrode of the pixel TFT, and in an inter-layer insulation film disposed on the insulation film in close contact therewith. These process steps use 6 to 8 photo-masks.