A mask plate is provided. The mask plate includes a first transparent substrate. A first transparent electrode, an electrochromic layer and a second transparent electrode are arranged sequentially on the first transparent substrate. The first transparent electrode is configured to be selectively powered so as to form energized regions with different shapes. A method for manufacturing the mask plate, a device including the mask plate, and a method for using the mask plate are further provided.

A display device and a method of manufacturing the same are disclosed. The display device includes a lower substrate, subpixels positioned on the lower substrate, and a fine alignment key positioned in at least one of the subpixels. The method of manufacturing the display device includes forming an alignment key outside a target substrate and forming a fine alignment key inside an active area defined as a display area on the target substrate, aligning the target substrate and a mask substrate using the alignment key and the fine alignment key, and performing an exposure operation using the target substrate and the mask substrate.

Embodiments of the disclosure provide an array substrate and a method for manufacturing the array substrate. The array substrate includes a substrate, a first electrode disposed on the base substrate and a second electrode disposed on the base substrate and located in a different layer from the first electrode with an insulation layer being disposed therebetween, wherein each of the first and second electrodes is a comb-like electrode, and the first and second electrodes are configured to generate an electric field therebetween when being applied with a voltage.

The present disclosure relates to a COA substrate including a glass substrate, a common electrode on the glass substrate, an insulation layer on the common electrode, a data line on the insulation layer, and the data line intersects with the common electrode. The COA substrate further includes a first passivation layer, a RGB color-filter layer, and a second passivation layer arranged on the data line in sequence. A disconnected gap is configured at an intersection of the common electrode and the data line such that the common electrode comprises two opposite ends. The insulation layer fills the gap, and the second passivation layer is configured with a conductive layer spanning over two ends of the common electrode. The present disclosure also relates to a liquid crystal panel including the above COA substrate.

An exposure mask includes an aligning portion and a boundary portion. The aligning portion may be aligned with pixel areas of a substrate and includes a first exposure member and a second exposure member. The boundary portion includes a first exposure element, a second exposure element, a third exposure element, and a fourth exposure element. The first exposure member, the first exposure element, and the second exposure element are positioned in a first row. The first exposure element is positioned between the first exposure member and the second exposure element and is larger than the second exposure element. The second exposure member, the third exposure element, and the fourth exposure element are positioned in a second row. The third exposure element is positioned between the second exposure member and the fourth exposure element and is smaller than the fourth exposure element. Each exposure member/element includes a light transmitter/blocker.

The present disclosure provides a method for manufacturing an array substrate and a display device. The method for manufacturing the array substrate includes providing a substrate; disposing a metal layer material on the substrate; disposing thermal reactive photoresist material on the metal layer material; obtaining a thermal reactive photoresist layer using a mask process and a thermal reaction process; and obtaining a metal layer by an etching process.

This disclosure discloses a display substrate, a production method for a display substrate, and a display panel. The display substrate comprises a display area and a preset seal area surrounding the display area, wherein the display area is provided with a plurality of spacers, and wherein the preset seal area is provided with a plurality of supports, the support and the spacer are provided in the same layer and are of the same material.

An array substrate includes a first light-shielding insulation layer formed on the substrate, for block a light entering the substrate, and including a first region and a second region, and each is made of an insulation material; a first function layer formed on the second region, under a light-shielding function of the second region, an affection of light is avoided; a second function layer formed above the first region of the first light-shielding insulation layer and the first function layer, under the light-shielding function of the first light-shielding insulation layer, an affection of light is avoided; and a third function layer formed above the second function layer, under the light-shielding function of the first light-shielding insulation layer, an affection of light is avoided; wherein, each of the first, the second and the third function layer is a conductor material or a semiconductor material. A photo-leakage current can be avoided.

A marked pixel unit includes at least one active element, a first dielectric layer, a color filter unit, a second dielectric layer, and at least one pixel electrode. The active element includes a source, a gate, and a drain. The first dielectric layer is configured to cover the gate. The color filter unit is disposed above the first dielectric layer, and has an alignment opening. The second dielectric layer is disposed above the active element and the color filter unit, and has a contact hole. The pixel electrode is disposed above the second dielectric layer, and electrically connected to the drain through the contact hole. The contact hole of the second dielectric layer is located outside the alignment opening.

A display device includes: a first substrate; a gate line on the first substrate, where the gate line extends in a first direction; a data line on the first substrate, where the data line extends in a second direction which intersects the first direction; a thin film transistor connected to the gate line and the data line; a passivation layer on the gate line, the data line and the thin film transistor, where the passivation layer includes a recessed portion; a light blocking portion on the recessed portion of the passivation layer; a main column spacer which protrudes upwardly from the light blocking portion; and a sub-column spacer which protrudes upwardly from the light blocking portion, where the sub-column spacer is spaced apart from the main column spacer.