A method of fabricating an array substrate is provided. The method includes providing a substrate including a gate pad configured to bond a gate driving integrated circuit, a data pad configured to bond a data driving integrated circuit, and a plurality of peripheral layout gate (PLG) proto-lines connecting the gate pad and the data pad; forming a PLG testing pad on the substrate; forming a shorting bar connecting the PLG testing pad to first terminals of the plurality of PLG proto-lines; forming a plurality of testing pins respectively connected to second terminals of the plurality of PLG proto-lines, wherein the plurality of testing pins are formed in a first dummy region of the substrate, the first dummy region is adjacent to an array substrate region of the substrate; and connecting the plurality of testing pins to a probe unit to test connectivity of the plurality of PLG proto-lines.

The present disclosure provides a shorting bar, a display panel, and a display device. The shorting bar includes test lines, wherein each test wire includes: a base substrate; an insulation layer disposed on the base substrate, wherein one or more via holes are formed in the insulation layer; one or more metal wires disposed in the insulation layer, wherein each of the metal wires are at least partially exposed in one of the via holes; and a conductive layer at least partially disposed in the via holes and covering the exposed metal wires, wherein the conductive layer is a strippable conductive layer.

A display substrate, a display device and a test method of the display substrate are disclosed. The display substrate includes a display region and a peripheral region. The peripheral region includes: a first leading wire extending in a first direction and including a first end and a second end; a first test wire electrically connected with the first leading wire at a first position of the first test wire between the first end and the second end; the display region includes first signal wires of first group extending in a second direction, two first signal wires arranged outermost in the first direction among the first signal wires of first group are respectively connected with the first end and the second end, and remaining first signal wires among the first signal wires of first group are connected with the first leading wire between the first end and the second end.

A display apparatus includes a substrate including a display area and a non-display area, a display element layer, a pad group, a touch electrode layer, and a touch insulation layer. The display element layer includes display elements disposed in the display area. The pad group is disposed on the substrate and includes output pads disposed in the non-display area. The output pads include central output pads and outer output pads disposed outside the central output pads in a first direction. The touch electrode layer is disposed on the display element layer. The touch insulation layer is disposed on the display element layer and contacts the touch electrode layer. A groove pattern is defined in the touch insulation layer overlapping the non-display area, and does not overlap at least a predetermined number of the outer output pads in a second direction.

A display panel, a method of making the same, and a display device are disclosed. The method of making the display panel includes: forming a display motherboard including at least one metal trace, the at least one metal trace being connected to all uncut display panels on the display motherboard; cutting the display motherboard along a cutting line to form at least two display panels, where the at least one metal trace is exposed on at least one side of each of the at least two display panels; dripping a concentrated acid solution to an exposed position of the at least one metal trace to react for a preset time, thus corroding the at least one metal trace at the exposed position thus forming an insulating metal salt structure.

A touch display apparatus is disclosed, which includes a touch display panel with an active area and a peripheral area. The touch display panel includes a substrate, touch electrodes, touch sensing lines, dummy touch sensing lines and transistors. The touch electrodes are disposed on the substrate and in the active area. Each touch sensing line is electrically connected to one of the touch electrodes. The touch sensing lines and the dummy touch sensing lines are in parallel with each other in the active area. The dummy touch sensing lines are electrically connected with each other. Each transistor has a first terminal, a second terminal and a control terminal. The first terminals of the transistors are electrically connected with each other, the second terminal of each transistor is electrically connected to one of the touch sensing lines, and the control terminals of the transistors are electrically connected with each other.

An array board 11b includes a display section AA, a source line 20 connected to the display section AA, a test circuit 40 connected to the source line 20 and configured to test the display section AA, a panel-side image input terminal that is disposed such that the test circuit 40 is between the terminal and the display section AA and to which a signal to be supplied to the source line 20 is input, a terminal connection line 51 connecting the source line 20 to the pane-side image input terminal 35A and the terminal connection line 51 including the terminal connection line 51 at least a part of which overlaps the test circuit 40 and a flattening film (insulation film) 28 at least disposed between an overlapping portion of the test circuit 40 and the terminal connection line 51.

Embodiments of the present disclosure provide a motherboard of an array substrate and a manufacturing method thereof. The motherboard of an array substrate includes a plurality of display areas and a plurality of non-display areas. The non-display area is located between adjacent display areas. The display area includes a first pixel unit configured for display. The non-display area includes a second pixel unit configured to test a characteristic of a thin film transistor on the motherboard of an array substrate. Through the second pixel unit, a characteristic of a thin film transistor on the non-display area may be tested, thereby being able to reflect a characteristic of a thin film transistor on the display area.

An example display apparatus includes: a display panel having a display region and a non-display region located at peripheries of the display region; a signal line provided in the display panel to transmit an image signal; a spare wiring routed to an outside of the display panel and the non-display region of the display panel, and connected to the signal line; a plurality of connection terminals; and an amplifier which have an input side connected to a first connection terminal and an output side connected to the spare wiring, and the display apparatus is configured to input a signal from the signal line to the amplifier through the first connection terminal. On the output side of the amplifier, a part of the spare wiring is connected to a second connection terminal, and is routed to the non-display region from the outside of the display panel. The part of the spare wiring is further connected a third connection terminal, and is routed to the outside of the display panel.

A display device includes a flexible substrate including a display area and a non-display area. The substrate has a first surface and a second surface opposite to the first surface. A first protection film is disposed on the first surface of the substrate. The first protection film is disposed over the display area of the substrate. A second protection film is disposed on the first surface of the substrate. The second protection film is disposed over the non-display area of the substrate. A light transmittance of the first protection film is higher than that of the second protection film.