According to one embodiment, a display device includes a first substrate, a second substrate and a liquid crystal layer. The first substrate includes a first insulating substrate, a scanning line, a signal line, a switching, and a pixel electrode. The liquid crystal layer includes a polymer in a shape of a streak and a liquid crystal molecule. The scanning line includes a conductive layer located between the first insulating substrate and the liquid crystal layer, and a first reflective layer located between the first insulating substrate and the conductive layer and having a reflectance higher than a reflectance of the conductive layer.

A display device includes a pixel matrix having pixel rows and pixel columns and including pixels having switching elements positioned alternately at a corner near an upper and a lower side of each pixel row and positioned alternately at a corner near an upper and a lower side of and alternately at a corner near a left and a right side of each pixel column; multiple pairs of gate lines transmitting a gate-on voltage; and multiple data lines transmitting data voltages, wherein each pair of gate lines are disposed at the upper and lower sides of each pixel row with the pixels in each row connected to the gate line positioned nearest the respective switching element, and each data line is disposed between adjacent pairs of pixel columns and connected to pairs of pixels where one pixel of the pair has a switching element positioned nearest the respective data line.

It is an object of the present invention to form a pixel electrode and a metal film using one resist mask in manufacturing a stacked structure by forming the metal film over the pixel electrode. A conductive film to be a pixel electrode and a metal film are stacked. A resist pattern having a thick region and a region thinner than the thick region is formed over the metal film using an exposure mask having a semi light-transmitting portion. The pixel electrode, and the metal film formed over part of the pixel electrode to be in contact therewith are formed using the resist pattern. Accordingly, a pixel electrode and a metal film can be formed using one resist mask.

A liquid crystal display includes a pixel electrode including a first subpixel electrode and a second subpixel electrode spaced apart with a gap therebetween, a common electrode facing the pixel electrode, and a liquid crystal layer formed between the pixel electrode and the common electrode and including a plurality of liquid crystal molecules. The first and second subpixel electrodes include a plurality of branches, and each of the first and second subpixel electrodes includes a plurality of subregions. The branches extend in different directions in different subregions.

Disclosed are an in-cell touch liquid crystal display (LCD) device based on a twisted nematic (TN) mode, a method of manufacturing the same, a method of manufacturing a thin film transistor (TFT) array substrate, and a method of manufacturing a color filter array substrate. The TFT array substrate includes a TFT disposed in a pixel area defined by an intersecting gate line and data line, a conductive line disposed on the TFT, and a transparent conductive layer in electrical contact with the conductive line. The color filter array substrate includes a light shield layer, a color filter, an overcoat layer covering the light shield layer and the color filter, a column spacer disposed on the overcoat layer, and a common electrode disposed on the overcoat layer and the column spacer, where the conductive line supplies the common electrode with a common voltage or a touch driving signal.

An array substrate includes a glass substrate GS, an alignment mark 29, and first traces 19. The glass substrate GS has a corner portion 30 having an outline defined by a first edge portion 11b1 and a second edge portion 11b2 crossing the first edge portion 11b1. The alignment mark 29 is disposed at the corner portion 30 and used as the positioning index in mounting a driver 21 and a flexible printed circuit board 13. The alignment mark 29 at least includes first and second side portions 29a, 29b parallel to the first and second edge portions 11b1, 11b2, respectively. One end of the second side portion 29b is continuous to one end of the first side portion 29a. The alignment mark 29 has an outline that is on a same plane with a reference line BL connecting other ends of the first side portion 29a and the second side portion 29b linearly. The first traces 19 include inclined portions 31 that are inclined with respect to the first and second side portions 29a, 29b along the reference line BL.

Disclosed are an oxide thin film transistor (TFT), a method of manufacturing the same, and a display panel and a display device using the same, in which a first conductor and a second conductor are provided at end portions of a semiconductor layer formed of oxide semiconductor. The first conductor and second conductor are electrically connected to a first electrode and a second electrode, and covered by a gate insulation layer. The oxide TFT includes a semiconductor layer provided on a buffer and including an oxide semiconductor, a gate insulation layer covering the semiconductor layer and the buffer, a gate electrode provided on the gate insulation layer to overlap a portion of the semiconductor layer, and a passivation layer covering the gate and the gate insulation layer.

A display device including a substrate, a gate line, a data line, a plurality of thin film transistors, a first pixel electrode, and a second pixel electrode. The gate line is disposed on the substrate. The data line is disposed on the substrate. The data line includes a first branch line and a second branch line. The first branch line and the second branch line form a closed loop. The plurality of thin film transistors is connected to the data line. The first pixel electrode is connected to at least one of the plurality of thin film transistors. The second pixel electrode is connected to at least another one of the plurality of thin film transisters. The first pixel electrode and the second pixel electrode are arranged in a substantially diagonal direction with respect to each another. The first branch line is connected to a source electrode of said at least one of the plurality of thin film transistors. The second branch line is connected to a source electrode of said at least another one of the plurality of thin film transistors.

A method of manufacturing, with high mass productivity, liquid crystal display devices having highly reliable thin film transistors with excellent electric characteristics is provided. In a liquid crystal display device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.

A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.