A method of controlling an isolated switching converter having an output voltage that is adjustable, can include: generating an output voltage setting signal characterizing an expected output voltage of a load; increasing a time period when an output voltage reference signal changes from a current value to the output voltage setting signal; and making overvoltage protection not trigger due to a change of the output setting signal.

The present disclosure relates to an apparatus for determining and/or monitoring at least one process variable of a medium in a containment, comprising a sensor unit and an electronics unit, wherein the electronics unit includes a transceiver unit and a transceiver protecting unit for limiting an input voltage of the transceiver unit to a first transceiver voltage value. According to the present disclosure, the transceiver protecting unit includes a first limiting unit and a transistor unit, the transistor unit connected in series with the transceiver unit, wherein the first limiting unit is connected in parallel with transceiver unit and to a control terminal of the transistor and is configured to control an input voltage for the control terminal of the transistor to a predeterminable control value such that the input voltage of the transceiver unit is limited to the first transceiver voltage value.

The present disclosure relates to an apparatus for determining and/or monitoring at least one process variable of a medium in a containment, comprising a sensor unit and an electronics unit, wherein the electronics unit includes a transceiver unit and a transceiver protecting unit for limiting an input voltage of the transceiver unit to a first transceiver voltage value. According to the present disclosure, the transceiver protecting unit includes a first limiting unit and a transistor unit, the transistor unit connected in series with the transceiver unit, wherein the first limiting unit is connected in parallel with transceiver unit and to a control terminal of the transistor and is configured to control an input voltage for the control terminal of the transistor to a predeterminable control value such that the input voltage of the transceiver unit is limited to the first transceiver voltage value.

In a general aspect, a circuit can include a pass device configured to receive an input voltage and provide an output voltage. The circuit can further include a current sink coupled with a control terminal of the pass device, the current sink being configured to discharge the control terminal of the pass device to limit the output voltage in response to the input voltage exceeding a threshold voltage. The circuit can also include a switch coupled in series with the current sink, the switch being configured to enable the current sink in response to the input voltage exceeding the threshold voltage.

A power control device includes: an output voltage controller configured to control an output voltage based on a feedback voltage corresponding to the output voltage; and an overvoltage protector configured to continue or stop the operation of the output voltage controller based on a first detection result of whether the output voltage has exceeded an output voltage threshold value and a second detection result of whether the feedback voltage has fallen to or below a feedback voltage threshold value.

A power control device includes: an output voltage controller configured to control an output voltage based on a feedback voltage corresponding to the output voltage; and an overvoltage protector configured to continue or stop the operation of the output voltage controller based on a first detection result of whether the output voltage has exceeded an output voltage threshold value and a second detection result of whether the feedback voltage has fallen to or below a feedback voltage threshold value.

A converter circuit converts AC electric power into DC power. An inverter circuit converts the DC power into AC power. A capacitor is connected in parallel to each of the converter circuit and the inverter circuit between these circuits. The capacitor allows variation of an output voltage from the converter circuit, and absorbs variation of an output voltage from the inverter circuit due to a switching operation. An overvoltage protection circuit includes a resistor and a semiconductor element connected in series to each other. The overvoltage protection circuit is connected in parallel to the capacitor to protect the inverter circuit from an overvoltage. First and second control units respectively control the inverter circuit and the overvoltage protection circuit.

In a power-supply device, a FET passes or blocks a current flowing from one side in a power-supply circuit. A current sensor detects a current flowing into the FET. A FET is coupled to the FET, and passes or blocks a current flowing from another side in the power-supply circuit. A current sensor detects a current flowing into the FET. A junction couples a load unit at a point between the FET and the FET. In each of switch units, a CPU controls the corresponding switch unit of the power-supply circuit based on the detection result detected by the corresponding current sensors.

A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.

A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.