A voltage regulator circuit for supplying a voltage to an input of a subsequent circuit element, the voltage regulator circuit comprising: a power supply, an output adapted to deliver a regulated output voltage, a first transistor connected between the power supply and the output for controlling the output voltage, a differential amplifier configured to provide a feedback to the first transistor, a protective circuit which is coupled to the gate of the first transistor and configured to control the first transistor, such that the turn-on of the first transistor is delayed and any overshoot output voltage is avoided at the output during an initial charging up phase after the power supply is turned on.

A voltage regulator circuit for supplying a voltage to an input of a subsequent circuit element, the voltage regulator circuit comprising: a power supply, an output adapted to deliver a regulated output voltage, a first transistor connected between the power supply and the output for controlling the output voltage, a differential amplifier configured to provide a feedback to the first transistor, a protective circuit which is coupled to the gate of the first transistor and configured to control the first transistor, such that the turn-on of the first transistor is delayed and any overshoot output voltage is avoided at the output during an initial charging up phase after the power supply is turned on.

A voltage detector has a diode ladder with one or more diodes connected in series between a battery voltage input and an upper measuring node. A measuring diode is connected between the upper measuring node and a lower measuring node. A resistor and a power-down switch are connected in series between the lower measuring node and a ground. An analog input to an Analog-to-Digital Converter (ADC) is connected by a switch to the upper measuring node to generate an upper digital value. Then the switch connects the analog input to the lower measuring node to generate a lower digital value. The difference between the upper and lower digital values is the diode voltage drop across the measuring diode and is multiplied by a number of diodes in the diode ladder and added to the upper digital value to generate a battery voltage measurement.

A voltage detector has a diode ladder with one or more diodes connected in series between a battery voltage input and an upper measuring node. A measuring diode is connected between the upper measuring node and a lower measuring node. A resistor and a power-down switch are connected in series between the lower measuring node and a ground. An analog input to an Analog-to-Digital Converter (ADC) is connected by a switch to the upper measuring node to generate an upper digital value. Then the switch connects the analog input to the lower measuring node to generate a lower digital value. The difference between the upper and lower digital values is the diode voltage drop across the measuring diode and is multiplied by a number of diodes in the diode ladder and added to the upper digital value to generate a battery voltage measurement.

A power control device includes: an output voltage controller configured to control an output voltage based on a feedback voltage corresponding to the output voltage; and an overvoltage protector configured to continue or stop the operation of the output voltage controller based on a first detection result of whether the output voltage has exceeded an output voltage threshold value and a second detection result of whether the feedback voltage has fallen to or below a feedback voltage threshold value.

A power control device includes: an output voltage controller configured to control an output voltage based on a feedback voltage corresponding to the output voltage; and an overvoltage protector configured to continue or stop the operation of the output voltage controller based on a first detection result of whether the output voltage has exceeded an output voltage threshold value and a second detection result of whether the feedback voltage has fallen to or below a feedback voltage threshold value.

A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.

A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.

A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits.

A low-dropout regulator includes a comparator for comparing a feedback voltage with a reference voltage to output a comparison signal, which corresponds to a comparison result, to a control node; an internal voltage generator coupled to the control node, and for generating the feedback voltage and an internal voltage based on the comparison signal; and a controller coupled to the control node, and for monitoring the internal voltage based on the comparison signal, and controlling a voltage level of the comparison signal according to a monitoring result.