G05F1/571

Method and apparatus for operating a power distribution system
11296491 · 2022-04-05 · ·

A method and apparatus for operating a power distribution system, includes providing a solid state switch downstream of a power source and upstream of an electrical load, the solid state switch operable in a conducting mode that enabling conduction from upstream to the output and a non-conducting mode that disables conduction from the input to the output, and providing a transient voltage suppressor defining a breakdown voltage upstream of the solid state switch.

Radiation tolerant temperature compensated delayed undervoltage lockout and overvoltage shutdown

A circuit includes a voltage detection path having a first transistor and a second transistor coupled to the first voltage detection path by a first terminal of the second transistor. The first voltage detection path includes: a first current source and a first voltage divider unit coupled to the first current source. The first transistor is coupled to the first voltage divider unit by a first terminal of the first transistor. A first voltage value at a second terminal of the first transistor is configured to switch between a first high voltage value and a first low voltage value at least partially based on a first detection voltage value provided at the first terminal of the first transistor by the first voltage divider unit. A second voltage at a second terminal of the second transistor is configured to switch between a second high voltage value and a second low voltage value at least partially based on the first voltage value at the second terminal of the first transistor.

Radiation tolerant temperature compensated delayed undervoltage lockout and overvoltage shutdown

A circuit includes a voltage detection path having a first transistor and a second transistor coupled to the first voltage detection path by a first terminal of the second transistor. The first voltage detection path includes: a first current source and a first voltage divider unit coupled to the first current source. The first transistor is coupled to the first voltage divider unit by a first terminal of the first transistor. A first voltage value at a second terminal of the first transistor is configured to switch between a first high voltage value and a first low voltage value at least partially based on a first detection voltage value provided at the first terminal of the first transistor by the first voltage divider unit. A second voltage at a second terminal of the second transistor is configured to switch between a second high voltage value and a second low voltage value at least partially based on the first voltage value at the second terminal of the first transistor.

Isolated switching converter, control circuit and control method thereof

A method of controlling an isolated switching converter having an output voltage that is adjustable, can include: sampling an output voltage of the isolated switching converter; setting an overvoltage protection threshold corresponding to the output voltage of the isolated switching converter when the isolated switching converter enters a protection mode; and triggering the overvoltage protection by comparing an output voltage feedback signal representing the output voltage against the overvoltage protection threshold.

Isolated switching converter, control circuit and control method thereof

A method of controlling an isolated switching converter having an output voltage that is adjustable, can include: sampling an output voltage of the isolated switching converter; setting an overvoltage protection threshold corresponding to the output voltage of the isolated switching converter when the isolated switching converter enters a protection mode; and triggering the overvoltage protection by comparing an output voltage feedback signal representing the output voltage against the overvoltage protection threshold.

POWER SUPPLY SEMICONDUCTOR INTEGRATED CIRCUIT
20220075403 · 2022-03-10 · ·

A power supply semiconductor IC includes: an output transistor connected between a voltage-input terminal and a voltage-output terminal; a control circuit that controls the output transistor based on a feedback voltage of an output voltage; a current-limit circuit that limits an output current of the output transistor such that the output current is not equal to or greater than a current limit; a first transistor constituting a current-mirror circuit with the output transistor; a short-circuit-fault detection circuit that detects a short circuit of the voltage-output terminal based on a voltage across a resistor connected in series to the first transistor; and a first output terminal that outputs a detection result of the short-circuit-fault detection circuit. The current limit is within a detection range of the short-circuit-fault detection circuit. The short-circuit-fault detection circuit detects a short circuit of the voltage-output terminal even while the current limit circuit limits the output current.

POWER SUPPLY SEMICONDUCTOR INTEGRATED CIRCUIT
20220075403 · 2022-03-10 · ·

A power supply semiconductor IC includes: an output transistor connected between a voltage-input terminal and a voltage-output terminal; a control circuit that controls the output transistor based on a feedback voltage of an output voltage; a current-limit circuit that limits an output current of the output transistor such that the output current is not equal to or greater than a current limit; a first transistor constituting a current-mirror circuit with the output transistor; a short-circuit-fault detection circuit that detects a short circuit of the voltage-output terminal based on a voltage across a resistor connected in series to the first transistor; and a first output terminal that outputs a detection result of the short-circuit-fault detection circuit. The current limit is within a detection range of the short-circuit-fault detection circuit. The short-circuit-fault detection circuit detects a short circuit of the voltage-output terminal even while the current limit circuit limits the output current.

PARALLEL LOW DROPOUT REGULATOR

A low dropout regulator includes a first stage that generate a first output voltage and a second stage that generates a second output voltage different from the first output voltage. The first stage and the second stage are coupled in parallel to a node, the stages are selectively controlled respective first and second output signals based on different conditions. One condition may be operation of a load in one or more predetermined modes. Another condition may be transition between modes. Selective control of the first stage during a mode transition may reduce voltage undershoot or voltage overshoot in the load.

PARALLEL LOW DROPOUT REGULATOR

A low dropout regulator includes a first stage that generate a first output voltage and a second stage that generates a second output voltage different from the first output voltage. The first stage and the second stage are coupled in parallel to a node, the stages are selectively controlled respective first and second output signals based on different conditions. One condition may be operation of a load in one or more predetermined modes. Another condition may be transition between modes. Selective control of the first stage during a mode transition may reduce voltage undershoot or voltage overshoot in the load.

SUPPLY VOLTAGE REGULATOR
20210311515 · 2021-10-07 ·

A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.