During its first and second residence times, corresponding first and second currents flow between a charge pump and a circuit that connects to one of the charge pump's terminals. Based on a feedback measurement from the charge pump, a controller adjusts these first and second currents.

A semiconductor circuit and a method of operating the same are provided. The semiconductor circuit comprises a first digital-to-analog converter configured to generate a first output current in response to a first binary code, and a second digital-to-analog converter configured to generate a second output current in response to a second binary code associated with the first binary code. The semiconductor circuit further comprises a first current-to-voltage converter configured to generate a first candidate voltage based on the first output current, and a second current-to-voltage converter configured to generate a second candidate voltage based on the second output current. The semiconductor circuit further comprises a multiplexer configured to output the target voltage based on the first candidate voltage or the second candidate voltage. The target voltage includes a configurable range associated with the second binary code.

A body bias voltage generating circuit includes a current mirror circuit configured to generate and input a target current to a target semiconductor element, the target semiconductor element configured to be set to a turned-on state; and a charge pump circuit including an oscillator configured to output a clock signal based on a result of comparing an output voltage of the target semiconductor element with a reference voltage, and at least one charge pump outputting a body bias voltage to each of a plurality of semiconductor elements, wherein each of the plurality of semiconductor elements is the same as or is the same type as the target semiconductor element.

A circuit for biasing a transistor is provided. The circuit includes an output terminal configured to be coupled to a gate terminal of the transistor and circuitry. In a first state, the circuitry is configured to output a control signal at a first voltage level for setting the transistor to a first transistor state. In a second state, the circuitry is configured to first output the control signal at a second voltage level different from the first voltage level following by changing the control signal from the second voltage level towards a third voltage level different from the first and second voltage level over time.

During its first and second residence times, corresponding first and second currents flow between a charge pump and a circuit that connects to one of the charge pump's terminals. Based on a feedback measurement from the charge pump, a controller adjusts these first and second currents.

A semiconductor device and a method for controlling body bias thereof capable of properly controlling body bias of a transistor even in a case where process variation occurs are provided. Operation speeds of ring oscillators ROSCn and ROSCp respectively change due to an influence of process variation at an NMOS transistor MN side and a PMOS transistor MP side. Speed/bias data represent a correspondence relationship between the operation speeds of the ring oscillators ROSCn and ROSCp and set values V1n and V1p of body biases VBN and VBP. A body bias controller receives speed values Sn and Sp measured for the ring oscillators ROSCn and ROSCp to which the body biases VBN and VBP based on default values are respectively applied, and obtains the set values V1n and V1p on the basis of the speed/bias data.

A control circuit and a delay circuit are provided. The control circuit includes a control unit and a feedback unit. The feedback unit is configured to output a feedback signal according to a voltage of the control unit and a reference voltage; a first terminal of the feedback unit is connected to a first terminal of the control unit, a second terminal of the feedback unit serves as an input terminal of the reference voltage, and an output terminal of the feedback unit is connected to a second terminal of the control unit. The control unit is configured to adjust a voltage of the second terminal of the control unit according to the feedback signal, so as to allow a current variation of the control unit with a first parameter to be within a first range.

Various implementations described herein are related to a device having header circuitry with first transistors that are configured to receive a supply voltage and provide a dynamically biased voltage. The device may include reference generation circuitry having multiple amplifiers that are configured to receive the supply voltage and provide reference voltages based on the supply voltage. The device may include bias generation circuitry having second transistors configured to track changes in the dynamically biased voltage and adjust the dynamically biased voltage by generating bias voltages based on the reference voltages and by applying the bias voltages to the header circuitry so as to adjust the dynamically biased voltage.

A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices.

Examples of the disclosure include a controller having a mode of operation including one of an on mode and an off mode, the controller including a voltage rail node, a reference node, at least one powered component configured to generate a bandgap voltage signal based on a rail voltage at the voltage rail node, a switching device coupled in series between the reference node and the at least one powered component and configured to provide a conductive path through the at least one powered component from the voltage rail node to the reference node in response to the controller being in the on mode, and to interrupt the conductive path through the at least one powered component in response to the controller being in the off mode.