In an embodiment, a voltage comparator includes: a first switch having a conduction terminal coupled to an internal node that is coupled to an output of the voltage comparator; a current source; a capacitor; and a second switch connected in parallel with the capacitor, wherein the current source, the capacitor, and the first switch are coupled in series.

Described embodiments include a circuit for controlling a voltage drop. The circuit includes a resistor coupled between an output voltage terminal and a reference voltage terminal. First, second and third switches each have respective first, second and third switch terminals. The respective second switch terminals are connected together and are coupled to the output voltage terminal. The respective third switch terminals are connected together and are coupled to the reference voltage terminal. A first transistor is coupled between a supply voltage terminal and the first switch. A second transistor is coupled between the supply voltage terminal and the second switch. A third transistor is coupled between the supply voltage terminal and the third switch. Control terminals of the first, second and third transistors are coupled to a gate control terminal.

Described embodiments include a circuit for controlling a voltage drop. The circuit includes a resistor coupled between an output voltage terminal and a reference voltage terminal. First, second and third switches each have respective first, second and third switch terminals. The respective second switch terminals are connected together and are coupled to the output voltage terminal. The respective third switch terminals are connected together and are coupled to the reference voltage terminal. A first transistor is coupled between a supply voltage terminal and the first switch. A second transistor is coupled between the supply voltage terminal and the second switch. A third transistor is coupled between the supply voltage terminal and the third switch. Control terminals of the first, second and third transistors are coupled to a gate control terminal.

A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

A constant voltage circuit includes a depletion transistor having a drain, a gate, and a source, the drain connected to a first power supply terminal, and the gate connected to the source, a voltage division circuit connected between the first power supply terminal and an output terminal, a first enhancement transistor having a drain connected to the source of the depletion transistor, a source connected to the output terminal, and a gate connected to an output terminal of the voltage division circuit, a second enhancement transistor having a source connected to the first power supply terminal, a drain connected to the output terminal, and a gate connected to the drain of the first enhancement transistor, and a pull-down element having one end connected to the output terminal and the other end connected to a second power supply terminal.

An apparatus is provided which generates a reverse bandgap reference using capacitive bias, which is applied to a single n-well diode. The capacitive bias allows for determining the current density precisely by pure timing control. An apparatus is also described for sensing temperature in which a forward-bias diode voltage can be sampled with a capacitor, and large current ratios are possible (e.g., ratio N greater than 1000). Duty cycle of a digital output of the sensor is used to determine the temperature sensed by the sensor.

A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.

Apparatus and methods are disclosed for providing a bias, comprising a bias generator circuit including a high voltage (HV) circuit configured to generate a regulated high voltage (HV) from an HV line and provide the regulated HV at an HV regulated line and a low voltage (LV) circuit configured to generate a low voltage (LV) differential from the HV line and to provide the LV differential at an LV line.

Apparatus and methods are disclosed for providing a bias, comprising a bias generator circuit including a high voltage (HV) circuit configured to generate a regulated high voltage (HV) from an HV line and provide the regulated HV at an HV regulated line and a low voltage (LV) circuit configured to generate a low voltage (LV) differential from the HV line and to provide the LV differential at an LV line.

A bias current generation circuit and a flash memory. The bias current generation circuit includes a voltage source, a switching circuit and a current generation circuit. The voltage source is configured to provide a voltage for generating a bias current. An input terminal of the switching circuit is connected to the voltage source, a control terminal of the switching circuit is configured to receive a control signal. The current generation circuit includes a first MOS transistor and a second MOS transistor, an input terminal and a control terminal of the first MOS transistor are connected to an output terminal of the switching circuit, an output terminal of the first MOS transistor is connected to an input terminal and a control terminal of the second MOS transistor, and an output terminal of the second MOS transistor is grounded.